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If you missed our recent seminar on Carrier Ethernet Equipment Design, you can now download the proceedings from the event, which include slides from all speakers. For a FREE copy of this material, access our web site. Neterion Samples Third-Gen 10GbE Adapters The key new feature of the X3100 Series is I/O virtualization. The controller's PCIe x8 interface supports the PCI-SIG's new single-root I/O virtualization (IOV) v1.0 specification. This interface is coupled with 17 internal virtual-NIC (vNIC) instances, which can be independently reset and managed as though they were physical NICs. In virtualized environments, implementing vNICs in hardware offloads this task from the hypervisor. Neterion is the first vendor to support VMware's NetQueue hypervisor offloads under ESX 3.5 and has demonstrated near-line-rate throughput in this environment. For non-virtualized servers running Windows, the X3100 adds support for large-receive offload (LRO). Neterion claims its hardware implementation of LRO delivers equivalent performance to the use of jumbo frames. With the introduction of the X3100 Series, Neterion has established technology leadership in I/O virtualization. This lead, however, could be short lived, as NetQueue support for current Intel and NetXen NICs is awaiting qualification. The X3100's new PCIe interface is of more immediate importance. Neterion is sorely late with a competitive PCIe NIC and has been losing business as a result. Server OEMs now have a reason to take a fresh look at Neterion for their next refresh cycle. —Bob Complete coverage of Neterion appears in our report A Guide to 10G Ethernet Adapters and Controller Chips.
Earlier this month, Intel and Via disclosed new x86 CPU architectures that can be used in embedded applications. Ironically, Via's new Isaiah design moves the low-cost vendor upscale, while Intel's Silverthorne targets very low power devices. Unlike recent Intel designs, Silverthorne has no instruction reordering or register renaming. Targeting clock speeds of up to 2.0GHz, the in-order CPU executes up to two instructions per cycle. But this is not your grandfather's Pentium. Silverthorne implements the latest 64-bit x86 instruction set with SSE3 extensions. It adds simultaneous multithreading, mixing and matching instructions from two threads to keep the dual-issue pipeline filled. The chip includes 512KB of level-two (L2) cache and a 533MHz front-side bus. Built in Intel's leading-edge 45nm technology, Silverthorne has been measured at worst-case power levels between 600mW and 2.0W, depending on clock speed. An external system-logic chip set, however, will add board area and power. Intel will announce pricing and availability of Silverthorne products later this year, but the chip's tiny die size (less than 25mm2) should enable low pricing. Using this new processor, Intel can for the first time target applications such as IP phones, consumer NAS and media servers, and portable equipment such as mobile Internet devices and ultramobile PCs. For smartphones and other handhelds, however, the new design is too power hungry and lacks the required level of integration. Via's C7 processor already serves many consumer applications, so the company aimed Isaiah at a higher performance point. The new design is Via's first to implement instruction reordering and can sustain three instructions per cycle. Scaling to 2.0GHz in 65nm technology, Isaiah is a full 64-bit x86 design compatible with the SSE3 extensions. The single-CPU chip also contains a 1MB L2 cache and, like other Via chips, a high-speed encryption unit. Via will announce pricing and other product details when the first Isaiah chips enter production later this spring. These products will compete with Intel's Celeron products in embedded (and PC) designs. —Linley Additional coverage of Intel and Via embedded x86 processors appears in our report A Guide to High-Speed Embedded Processors.
At the recent Mobile World Congress, both Cavium and RMI (formerly Raza Microelectronics) announced new processors targeting cellular infrastructure, although the devices can also be used in other embedded applications. Cavium's CN5200 family is the newest iteration of its Octeon Plus product line. The new products feature 2 to 4 MIPS64 CPUs at speeds of up to 900MHz. They include 512KB of L2 cache, encryption acceleration, four Gigabit Ethernet (GbE) MACs, and four lanes of PCI Express (PCIe). Pricing ranges from $50 to $120 for the new processors, which are due to sample in 2Q08 and enter production shortly thereafter. Cavium positions the CN5200 for 3.5G and 4G basestations, which require a high level of processing and typically use Ethernet uplinks. The Octeon line also scales to 16 CPUs for radio network controllers and down to single-CPU devices for pico-basestations. Cavium claims to have more than 30 design wins in cellular infrastructure, including basestation designs from ZTE and Qualcomm. The CN5200 can also be used in SMB storage applications; some models include RAID acceleration. RMI announced new versions of its XLS processor, the 416 and 616. Both have 4 MIPS64 CPUs at speeds of up to 1.2GHz. Each XLS CPU is four-way multithreaded, so the new chips offer 16 virtual CPUs. The new devices include 1MB of L2 cache, encryption acceleration, eight GbE MACs, and four lanes of PCIe. Unlike Octeon, these devices support IEEE 1588, enabling synchronized timing control on the Ethernet uplink. RMI's chips also support serial RapidIO, a popular method of connecting to DSPs in wireless basestations. RMI did not disclose pricing for the new devices, which are due to sample in 3Q08. The new XLS processors offer slightly more performance and more GbE MACs than the new Octeons, although Cavium offers higher-end Octeons as well. The key differences are RMI's support for RapidIO and IEEE 1588. Although many basestations do not require these features, the new XLS is ideal for those that do. —Linley Detailed coverage of the Octeon and XLS processors appears in our report A Guide to High-Speed Embedded Processors. This month, Aquantia raised $26 million in its second round of funding. The startup is developing a 10GBase-T PHY, but it has not yet made any product announcements. We believe the startup has received its first silicon and is sampling the device to beta accounts. We believe this PHY to be a single chip dissipating significantly less power than announced products from Teranetics and Solarflare. We expect Aquantia to announce its product by mid-2008, becoming the third vendor to sample a 10GbE PHY for copper media. Aquantia's funding follows large funding rounds at competing 10GbE PHY vendors such as Solarflare and Plato Networks. The amount of venture capital rolling into 10GBase-T PHYs underscores the importance of this market. —Jag Additional coverage of 10GBase-T PHYs appears in our report A Guide to Ethernet Switch and PHY Chips.
If you are using or evaluating intellectual property (IP) for your ASIC or SoC (systems on a chip) device designs, then you won't want to miss our next Linley Tech seminar. Join us on March 19 in San Jose when we bring together industry leaders to discuss the latest developments in CPU cores and other licensable intellectual property (IP) for networking and communications applications. This one-day event delivers a wealth of information including technology trends, tips, and traps in using and understanding the IP blocks available from leading vendors. Our outstanding lineup of technical presenters, includes:
Admission is free to qualified attendees who register by March 14. The seminar is targeted at ASIC and SoC designers, OEMs, press, and the financial community. Visit our web site for details. This Linley Tech seminar is sponsored by Freescale, IBM, Tensilica, SafeNet, and T-RAM. To receive Linley Wire via e-mail, click here
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