The Linley Wire
Independent Analysis of the Networking-Silicon Industry

Volume 8, Issue 5
March 12
, 2008

Editor: Linley Gwennap
Contributors: Bob Wheeler, Jag Bolaria, Joseph Byrne

In This Issue


Time is running out; register this week to reserve your place! On March 19, our Linley Tech seminar will illustrate how CPU cores and IP for high-speed transceivers, security accelerators, and high-performance memory can be integrated into ASICs and SoCs. The seminar is free to qualified ASIC and SoC designers at chip suppliers and OEMs. Sponsored by Freescale, IBM, Tensilica, SafeNet, T-RAM, and EEMBC. For further details and registration, visit our web site.

Cortina Launches 40Gbps Framer/Mapper

At the recent Optical Fiber Communication Conference (OFC), Cortina launched an OC-768 POS framer mapper, the CS1999. The device targets carrier-class core routers such as Cisco’s CRS-1 and Juniper’s T640. It terminates SONET/SDH section and performs line and path overhead processing. The device integrates a TOH/POH processor along with a POS mapper. The CS1999 also includes diagnostic features such as generating and monitoring packets at full line rate.

The CS1999 includes serdes for the line interface as well as for the system interface. The line side complies with OIF’s SFI-5.01 interface, a 16-bit interface operating at 2.488Gbps. The serdes includes CDR for the receiver and a PLL multiplier for the transmitter. SFI-5.01 connects directly to a 40Gbps optical module. For the system side, the serdes are configured to the Interlaken specification. Interlaken can be configured as 8, 10, 12, or 16 lanes operating at 6.25Gbps each and supports flow control. In a line card, Interlaken typically connects to a network processor or Layer 3 forwarding ASIC.

The new 40Gbps framer adds to Cortina’s transport product line, which includes OC-192, OC-48, and OC-3 framers. The company is already shipping PHYs to Cisco and other router vendors. Cortina can leverage its installed base of transport products to win designs for its new framer. The CS1999 is currently sampling and has a typical power dissipation of 16W. Although Cortina is not the first vendor to announce an OC-768 framer, the new product’s feature set and timing are well suited for current carrier-class routers. —Jag

Save the date! Mark your calendars for May 14 for a Linley Tech seminar on High-Speed Interconnects. This event will cover chip-to-chip and 10G Ethernet interconnects. Details on this event will be announced soon.


Cool EDC Chips at OFC

Last month, Cortina announced a family of EDC (electronic dispersion compensation) components for 10G Ethernet. The CS4212 is designed to operate with SFP+ modules and is rated to support more than 300m of multimode fiber. The device integrates four CDRs and two EDC circuits to support two SFP+ modules—improving port density per line card. The device does not require an external microcontroller to control convergence or dynamic adaptation of dispersion compensation. Depending on the system design, this could reduce the system cost. With a typical power dissipation of 1.5W, the CS4217 is similar to the CS4212 but instead targets X2 and XFP modules. In 1Q08, Cortina expects to ship more than 40,000 ports using these devices. We believe the end customer is Cisco, which uses these devices in a non-EDC mode.

At OFC, Inphi introduced the 3200EC dual CDR with EDC for 10GBase-LRM. The device is designed for use in XFP modules, and Inphi claims its device to be the first to comply with LRM standards for XFP. XFP modules with the 3200EC can be used for 10G Ethernet backhaul on legacy multimode fiber. The device provides an XFI interface for the system side as well as equalization and pre-emphasis. For the line side, it works with TIAs from Inphi or third parties. The 3200EC integrates a microcontroller and non-volatile memory to enable standalone operation at less than 2.5W of power.

Also at OFC, Phyworks announced availability of its 10GBase-LRM CDR and EDC component. The PHY2060 includes adaptive equalization and pre-emphasis to enable operation inside XFP/X2 modules as well as alongside SFP+ modules. The chip supports transmission of up to 300m over multimode fiber. The PHY2060 includes algorithms to deal with dynamic stressors and removes the need for an external microcontroller. The company demonstrated margin to the three stressors (pre-, post-, and dynamic) that are often used in industry tests. For end-to-end loop testing, the chip includes a PRBS generator and a BER detector. The PHY2060 is sampling in a 5mm BGA package and has a typical power dissipation of less than 1W.

OEMs now have several options for EDC components. Although other vendors have previously announced EDC devices, problems with these early devices have prevented high-volume deployments. Vitesse was the first to offer parts that met specifications for the different stressors. These devices, however, had high power dissipation and required an external microcontroller for configuration. The new devices do not need an external microcontroller and reduce power dissipation. All of the suppliers claim compliance with specifications, but few have shared performance numbers to validate these claims. Although OEMs have multiple vendors providing low-power EDC components, the winners will separate themselves on the basis of performance to industry standard stressors. Once performance is proven, volume for EDC components should increase. —Jag

Additional coverage of EDC appears in our report A Guide to Ethernet Switch and PHY Chips.


Lightwire Demos Silicon Photonics

On Feb 25, Lightwire demonstrated its first product and outlined a roadmap to 100Gbps. The company’s first product is a 10Gbps SFP+ module for LRM applications. The LSM10XX module uses CMOS photonics to reduce power dissipation and drive distances of up to 220m. Lightwire uses a patented SISCAP silicon structure to change the wavelength of light at lower power dissipation than competing solutions. Lightwire’s device splits light into two beams and uses its SISCAP structure to shift the phase of the wavelength in each beam. Depending on the phase shift, the combined light from the two beams is either canceled out or amplified, creating a logical zero or one.

Lightwire developed two devices for the SFP+ module. The first is an optical modulator developed on 130nm technology. The second is a signal conditioner developed on 65nm technology. The signal conditioner includes circuits for CDR, TIA, LA, driver, and receiver. Partitioning the functionality into two devices reduced development risk and time to market. Lightwire worked with IME to develop the silicon on standard process technologies at Chartered Semiconductor.

The company’s initial products target enterprise application with SFP+ LRM, which use 1310nm wavelength light. By mid-2008, Lightwire plans to offer modules at the 1550nm wavelength, which is used for long (40km) distances. The company has no plans to address low-cost SR modules, which use 850nm light. Instead, Lightwire plans to offer active cables later in 2008 and 40Gbps modules further out in time. With standards-based modules at less than 400mW, Lightwire offers compelling solutions that can help OEMs increase port density today with scalability in the future. —Jag


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Communications semiconductor product categories covered in the report include network processors, Gigabit Ethernet components, DSL and PON transceivers, security processors, and Sonet ICs. The report also includes market share for switch fabric and interconnect chips and for high-end embedded microprocessors. Among the scores of companies covered are established suppliers—such as Broadcom, Freescale, Infineon, LSI, NetLogic, and Texas Instruments—and smaller companies such as Cortina and Neterion.

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