Editor: Linley
Gwennap In This Issue
A Guide to Security Processors and Accelerators is now available. Get the latest information on processors that integrate high-throughput encryption, VPN and SSL accelerators, and content-inspection accelerators. Click here for more information. At its technical conference last week, Freescale unveiled its next-generation processor family under the name QorIQ (pronounced Core IQ, but don't tell Intel that). The new Power processors, the first of which will sample late this year, will all be built in 45nm technology and use the company's popular e500 CPU. Different models include from one to eight of these CPUs. The flagship product is the P4080, which combines eight 1.5GHz CPUs with a set of hardware accelerators for encryption, pattern matching, and packet processing that are similar to those in the current MPC8572. Each CPU has its own 128KB L2 cache, and all share 2MB of L3 cache. The chip also integrates plenty of high-speed memory and I/O controllers. Even with all of these features, the company expects maximum power dissipation will be less than 30W for the P4080, which is due to sample in 2Q09. Freescale also announced several lower-power processors targeting SMB and access infrastructure. These products have one or two CPUs at speeds ranging from 400MHz to 1.2GHz, encryption and RAID XOR accelerators, and a more limited set of I/O options. Even the dual-CPU parts will dissipate less than 7W (maximum), and list pricing for single-CPU versions starts at $23. These products are slated to sample in late 2008 or early 2009. Over time, the company will fill out the product line with additional devices. The new products thrust Freescale into the multicore race. Although Cavium offers up to 16 CPUs on a chip, Freescale's CPUs are more powerful, and the P4080 is likely to outperform Cavium's current parts. Even if Cavium delivers a faster device by the time the P4080 samples, Freescale will be competitive for almost all of the multicore applications that Cavium and RMI dominate today. Current PowerQuicc II customers will enjoy the speed boost from the low-end QorIQ products, which take advantage of the jump from 90nm to 45nm. Having preannounced its next generation, Freescale's challenge is to execute well and deliver the new products as planned. —Linley Additional coverage of Freescale's processors appears in our new report A Guide to High-Speed Embedded Processors.
At last week's NXTcomm08 conference in Las Vegas, a significant number of chip vendors announced or demonstrated their latest wares for carrier networks. After years of reduced investment, optical transport is seeing a new wave of chip introductions. The common denominator among these offerings is the ability to carry 10Gbps traffic over G.709 OTU-2 using forward error correction (FEC). AMCC, the leader in first-generation FEC chips, demonstrated its new Pemaquid device connected to client ports through Marvell's new Prestera 98DX4100 GbE switch chip. A survivor of the optical downturn, startup Galazar Networks announced its MXP2 device. Whereas Pemaquid has a single XAUI client port, the MXP2 multiplexes a variety of traffic types from up to 10 client ports into a pair of OTU-2 ports. Finally, intellectual-property vendor TPack demonstrated its new OTN/FEC core. Implemented in an Altera Stratix III FPGA, TPack's TPOX3203 combines the new block with a carrier-Ethernet switching engine to aggregate 12xGbE ports into an OTU-2. Other 10G Ethernet announcements included new chips from Vitesse and Fulcrum. The Vitesse VSC7350 is a 2x10GbE MAC aggregator with one SPI-4.2 host port. The VSC7350 can channelize its dual XAUI ports into up to 48 channels on the SPI port. For example, the VSC7350 can aggregate 48xGbE ports from a pair of attached VSC7344 MAC chips. Targeting ATCA and other backplane designs, Fulcrum's FM3000 is a 24x10GbE Layer 2+ switch with advanced congestion-management features. An impressive 100G Ethernet technology demo came not from a chip vendor but rather from test-equipment vendor IXIA. Using a pair of prototype testers, IXIA demonstrated a pre-standard 100GbE implementation passing 150 million packets per second in each direction! The 100GbE MAC, implemented in FPGAs, connected to an Avago optical module using the proposed multilane distribution (MLD) PCS layer. MLD stripes the 100Gbps flow across multiple lanes, in this case 10x10Gbps lanes for parallel fiber. Although the 100GbE standard won't be complete before mid-2009, the IXIA demo shows network-equipment vendors can begin building prototypes today. Following an excruciatingly long wait, 10Gbps optical links are finally driving real volume for chip vendors. Although legacy Sonet/SDH had too many chip suppliers, relatively few vendors are investing in new 10Gbps and faster designs. This consolidation should result in a smaller but healthier ecosystem of chip vendors. —Bob Additional coverage of 10GbE chips appears in our report A Guide to Ethernet Switch and PHY Chips. Last week, VirtenSys demonstrated its I/O virtualization technology over a standard PCI Express (PCIe) interconnect using native PCIe adapters. The company's products will support Single-Root IOV (SR-IOV) as well as Multi-Root IOV (MR-IOV). The company claims its technology will improve I/O utilization by 80% while reducing cost and power consumption by up to 50%. The unique aspect of this product is that it lets OEMs use existing PCIe I/O cards and therefore existing software stacks. VirtenSys plans to offer products that virtualize and share off-the-shelf Ethernet, Fibre Channel, and SAS/SATA PCIe adapters. Supporting existing I/O adapters has the potential to reduce cost when compared with MR-IOV adapters. VirtenSys plans to offer switch-card modules and complete systems to OEMs and systems integrators. —Jag Recently, PLX Technology expanded its PCI Express products with a family of control-plane switch chips. The new PEX8618, PEX8614, and PEX8608 chips offer 16 ports, 12 ports, and 8 ports, respectively. Each device supports PCIe v2.0 and has the same number of lanes as ports. Allowing the PCIe lanes to be segmented across a large number of ports positions these devices for control-plane applications. The company differentiates its products through performance features and diagnostic capabilities. Performance features include intelligent bandwidth allocation, simultaneously sending data to two ports, and dynamically allocating buffers. The diagnostic capability allows system designers to inject noise and measure the signal quality to evaluate the system's ability to detect and recover from errors. —Jag Additional coverage of PCI Express products appears in our recent report A Guide to High-Speed Interconnects.
Are you responsible for designing security into networking systems? If so, then you won't want to miss our July 16 Linley Tech seminar on Embedded Network Security Design. The seminar is intended to deliver critical information needed by engineers or engineering managers responsible for designing network-security equipment or designing security into switch/routers or other equipment. The program features technical presentations from leading suppliers of products for this market. We have an outstanding lineup of technical presenters, including:
The seminar, free to qualified attendees who register by July 11th, is intended for system designers, OEMs, network-equipment vendors, service providers, security-software vendors, press, and the financial community. Attendees will have the opportunity to discuss their specific issues with the speakers and vendors during lunch and the reception. As a special bonus, we're giving away an Apple iPod and a copy of The Linley Group's brand-new report, A Guide to Security Processors and Accelerators. The seminar will be held at the DoubleTree Hotel in San Jose, CA. Visit our web site for details. Sponsored by Freescale, AMCC, Netronome, LSI, SafeNet, Cavium, and cPacket. To receive Linley Wire via e-mail, click here
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