Editor: Linley
Gwennap In This Issue
A Guide to to Access Processors will soon be available. Don't miss our detailed coverage of the newest products and latest vendors in this dynamic market. For more information, visit our web site. Cavium Announces Multicore MIPS Processor Today, Cavium announced a family of integrated security processors with throughput up to 10Gbps, based on a custom 600MHz 64-bit MIPS-compatible core. The four family members range from the two-core CN3420, at $125, to the 16-core CN3860, at $750. These are the first devices to address a complete set of Layer 3–7 security functions in a single chip. They are expected to sample in 1Q05. With encryption increasingly becoming an integrated feature,
the move towards integrated multilayer security is an inevitable
one
for security-processor vendors—and a formidable challenge.
One problem is that processing upper-layer payloads requires a
full TCP proxy implementation, itself a daunting task at 10Gbps.
The other problem is that upper-layer content processing tends
to be very software-intensive and therefore difficult to accelerate. Other security vendors are also moving towards multilayer security processing. Layer N Networks was first to market with an SSL processor that provides a full TCP proxy, but that chip has no general-purpose processors. Last year, Corrent announced a MIPS-based multilayer security processor with only 200Mbps throughput. Hifn, which acquired the IBM nPower NPU line, is likely to leverage that technology to create a multilayer security processor. Cavium’s Octeon, however, is the first open-architecture effort, which will attract customers with existing Pentium-based content-processing applications seeking to deliver multi-Gigabit throughput. Cavium’s recent acquisition of MIPS-based communications processors from Brecis provides code-compatible entry-level processors in the Octeon line. Cavium has assembled the elements of the broadest security-processor line in the industry; if the company can deliver the full breadth of Octeon, it will take security processing to a new level. —SI Complete
coverage of Cavium’s other security processors appears
in our report A Guide to Security and Content Processors.
Last week, Parama Networks introduced a 10Gbps ADM on a chip (AoC), complementing its earlier AoC that offer capacities of 160Gbps and 40Gbps. The newest device, the PNII8010, allows Parama to address lower-speed Sonet services for applications such as an OC-48 MSPP (multi-service provisioning platform) or a digital cross-connect. Unlike current solutions that perform Sonet framing on the line card, Parama’s architecture centralizes much of the Sonet overhead processing and switching. By moving the framer and switching function from multiple line cards to a switch card, Parama plans to reduce the cost of an ADM by more than five times. The PNI8010 includes two OC-48 line ports that would connect to the Sonet ring and 8 OC-12 tributary ports that are added or dropped towards the Sonet network. It integrates a 10G cross-connect for switching between the line ports and tributary ports at a granularity of STS-1. The PNI8010 performs Sonet framing functions such as synchronization, scrambling, parity calculation, and error detection on each port. Manufactured in UMC’s 0.13-micron technology, the PNI8010 is scheduled to sample later this month. With a power dissipation of 4W, this device should be attractive for pizza-box configurations. The high integration of the PNI8010 and lower system cost make it attractive for new system designs. Although the PNI8010 reduces system cost, it locks the OEM’s system architecture for the product’s lifecycle – typically more than 5 years. Because OEMs are reluctant to make a startup the hinge factor for their roadmap, Parama must develop a broader roadmap and a strategy for long-term viability to secure major designs wins. —JB Complete
coverage of Parama’s products appears in our upcoming report
A Guide to Next-Generation Sonet Silicon.
Marvell has extended its Prestera-DX line of Ethernet switches with devices that support 10GbE uplinks and stacking. At the top of the line is the new 98DX270, a 24xGbE switch with three integrated 10Gbps ports. The uplink ports operate in either a standard XAUI mode or in a proprietary stacking mode that Marvell call’s HyperG.Stack (HGS). HGS mode adds features such as cross-stack link aggregation, policing, and VLANs. The ports can also be configured to run at 12Gbps in HGS mode, allowing two uplinks to service 24 GbE ports without oversubscription. Thus, Marvell claims the DX270 is a 60Gbps switch (24x1G+3x12G). The company is also offering 24xGbE+2x10GbE (DX260) and 24xGbE-only (DX250) versions of the new switch. Compared with Marvell’s existing 24xGbE switch chip (DX241), the new chips offer many new features. Whereas the DX241 is an unmanaged design, the DX250/260/270 add a management port with a choice of PCI or GMII/RGMII interfaces. A new integrated TCAM enables packet classification for QoS and security functions such as DiffServ marking and ACLs. All three versions of the new switch come in a 37.5mm BGA package. The DX270 dissipates a maximum of 8W, while the GbE-only DX250 requires only 5W. The DX250/260/270 are currently sampling; pricing was not announced. With its new Prestera devices, Marvell has upped the ante for stackable-switch designs. Although Vitesse was first to offer a 24xGbE+2x10GbE switch chip, that chip lacks integrated XAUI transceivers and does not offer stacking features. Meanwhile, Broadcom’s StrataXGS chips offer stacking features but trail in integration with only 12 GbE ports plus one uplink per device. If Marvell can quickly move its new DX chips to production, it will retake the technology lead in an important and fiercely competitive segment. —BW Complete
coverage of Marvell’s GbE-switch chips appears in our report
A Guide to Gigabit Ethernet Silicon. EZchip has announced two low-cost versions of its upcoming NP-2 network processor. Whereas the high-end NP-2 is a 10Gbps full-duplex device with integrated traffic manager, the NP-2/5 is a 5Gbps full-duplex device suitable for 2xOC-48 line cards or various GbE designs up to a maximum of 10xGbE with oversubscription. The NP-2/10L has no traffic managers, making it a more direct replacement for the current NP-1c in cut-through designs. The NP-2/5 and NP-2/10L are priced at $445 in volume. Samples of all NP-2 variants are due in 4Q04. —BW Complete coverage of EZchip products appears in our report A Guide to Network Processors. Intel has upgraded its Centrino notebook platform with an optional 802.11a/g Wi-Fi module. The new PRO/Wireless 2915ABG Mini PCI module adds 5GHz support but is otherwise similar in design to Intel’s 802.11g (2200BG) module. The 2915ABG is priced at a small premium over the 2200BG; OEMs can choose to standardize on one module or to offer customers both options. Perhaps equally important is a new version 9.0 of Intel’s PROSet/Wireless software, which runs on both the 2915ABG and 2200BG cards. The new software adds support for WPA2 (802.11i) security and WMM (802.11e) QoS. —BW Complete coverage of Intel’s Wi-Fi chips appears in our report A Guide to Wireless LAN Chip Sets. Last week, Agilent announced the 4Q04 sampling of a new 4G FC controller, the quad-channel HPFC-6400A Tachyon QX4. Without providing a date, Agilent also promised a 2G FC version of Tachyon QX4. The Tachyon QX4 makes use of an eight-lane PCI Express bus to provide sufficient host bandwidth. The Tachyon QX4 supports end-to-end data reliability by implementing the T-10 Data Integrity Field (DIF), a special tag that resides with data on the storage medium and detects corruption during storage or transport. Agilent has not announced performance in IOPS or pricing for Tachyon QX4. —SI Complete
coverage of Agilent’s
FC controllers appears in our report A Guide to Storage Networking
Silicon. We're excited to introduce an-all new report focused exclusively on next-generation Sonet. A Guide to Next-Generation Sonet Silicon provides in-depth coverage on the newest products and vendors for framers/mappers and add/drop multiplexers (ADM) designed for network edge and metro network applications. Sonet networks, originally designed to accommodate voice communications, have been faced with the challenge posed by the massive growth in communications bandwidth. This growth is largely fueled by demands for data services that have distinctly different characteristics than voice making the Sonet network inefficient for data transport. To address this growth, the industry has specified new standards for virtual concatenation and link capacity adjustment. This report examines mappers for Ethernet, FC, and RPR as well as ADM chips. Although some of these devices were designed to also support native RPR or long-haul Ethernet, most are optimized to use the existing Sonet network. Most of these devices can encapsulate any type of data using GFP (Global Framing Protocol) and perform VCAT (virtual concatenation) and LCAS (link capacity adjustment scheme). Get extensive coverage of next-generation silicon from Agere, PMC-Sierra, AMCC, Vitesse, Cypress, Infineon, Alliance, and TranSwitch. The report also covers competing silicon from startup vendors such as Galazar, Parama, and Arrive Technologies. "A Guide to Next-Generation Sonet Silicon" is packed with over 100 pages of crucial information you need to understand these hot technologies. We explore the target markets and relevant applications, then analyze each product, providing clear explanations of their architectures and features. Unlike typical market research, "A Guide to Next-Generation Sonet Silicon," provides analysis of the underlying technology and business strategies rather than quantitative market data. We provide the forward-looking view you need to determine winners from also-rans. Order by October
8, 2004 to get a special prepublication
discount. To get more information on this report, visit
our web site. Linley's Latest Column: EE Times: Needed: Smarter NICs
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