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A Guide to Network Processors

Thirteenth Edition

Published July 2012

Authors: Bob Wheeler and Jag Bolaria

Single License: $3,495 (single copy, one user)
Corporate License: $5,000

Pages: 160

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The Definitive Report on Network Processing

NPUs have become a critical ingredient of carrier-equipment designs. These chips are appearing in new designs from leading OEMs spanning many applications from wireless backhaul to Carrier-Ethernet switch/routers. This broad adoption has created a merchant market that exceeded $350 million in 2011, large enough to sustain multiple vendors. Following years of market growth and vendor consolidation, only a single NPU startups remain, while all other active vendors are public companies.

Access infrastructure is migrating to Ethernet and IP backhaul while data rates for both wireline and wireless networks continue to climb. These factors are driving the need for new access NPUs with throughputs of 10Gbps or more. Meanwhile, metro-class NPUs are scaling to 100Gbps and beyond to support high-density line cards and emerging 40G/100G Ethernet. A "Guide to Network Processors" provides a single comprehensive report covering NPUs spanning data rates from 10Gbps to 200Gbps.

This report covers customer-programmable NPUs for access and Carrier Ethernet designs, including: Broadcom’s XGS Core and Dune lines, LSI’s Axxia line, PMC-Sierra's (Wintegra) WinPath, EZchip's NPA and NP lines, Netronome's NFP (Intel IXP derivative), and Marvell's Xelerated HX and AX lines. We also cover Ethernity, which offers FPGA-based chips that compete with NPUs in some designs. This report also includes coverage of search coprocessors, such as Broadcom’s (NetLogic’s) KBP products, which are often used with high-end NPUs. 

Only The Linley Group follows this market closely enough to give you the complete picture. Which vendors are in this business for the long haul? How do the latest products stack up? What is the market outlook for merchant NPUs?  "A Guide to Network Processors" is the result of years of research that cannot be duplicated. If you are interested in following this strategic standard-product segment, you have located the definitive source.

Get Facts, Not Fiction

This report cuts through the vendor hype and gives you the solid information you need to understand this market. "A Guide to Network Processors" analyzes each vendor and each product, probes their strengths and weaknesses, then presents key details in a consistent, easy to compare fashion. For those less familiar with this combination of networking and CPU design, the report includes several introductory chapters that define and describe basic concepts and key technologies.

The Linley Group is the most recognized and respected name for technology and market analysis of network processors. Don't be fooled by weak overviews written by market analysts who really don't understand how a network processor works. The "Guide" provides a unique combination of business and technology savvy from the leading analysts in this market. Bob Wheeler and Jag Bolaria use their long experience in the networking world to analyze these devices. Together, the two authors ignore the fiction and provide the real story on each NPU vendor and its products.

Don't miss the latest information on this important market. Order now.

This report is written for:

  • Engineers who are designing networking equipment and need to select a network processor (NPU)
  • Marketing and engineering staff at companies that sell NPU products who desire competitive information
  • Technology professionals who want an introduction to networking and network processors
  • Financial analysts who desire a detailed analysis and comparison of NPU companies and their chances of success
  • Network architects at carriers and service providers who need to get up to speed on this technology

What's New in This Edition

Updates to the 13th Edition of "A Guide to Network Processors"

A Guide to Network Processors" has been extensively updated to include the latest disclosures from NPU vendors as well as 2011 market data.

Here are some of the many changes you will find:

  • New quantitative market data, including:
    • NPU-vendor market shares for 2011
    • Search coprocessor vendor market shares for 2011
    • NPU market segmentation by application
    • Forecasts for merchant NPUs and search coprocessors through 2016
  • Coverage of Broadcom’s new BCM 88030 (Caladan3) NPU and BCM88645 packet processor and TM/FIC
  • Coverage of EZchip’s new NP-5 200Gbps NPU/TM.
  • Coverage of LSI's new Axxia AXM2500
  • Coverage of Netronome's new NFP-6xxx 200Gbps NPU
  • New Marvell chapter incorporating the former Xelerated NPUs
  • New Cavium section covering the Neuron Search algorithmic search coprocessor 
  • Extensive updates to company-background information, roadmaps, and analysis for major NPU vendors
  • Revised and updated tutorials.





All Tier One networking and communications OEMs use NPUs in a range of systems, including edge/services routers, Carrier Ethernet switch/ routers (CESRs), optical-transport platforms, and wire­less and broad­band infrastructure equipment. Many of these OEMs continue to invest in internal NPUs, which will limit the adoption of merchant products. But even those with internally developed NPUs, such as Alcatel-Lucent, Cisco, and Juniper, are using merchant NPUs in some designs.

After weathering the global eco­nomic crisis in 2009, the NPU market in 2010 posted its highest growth rate in four years. For 2011, revenue dipped slightly, but it was still 21% greater than in 2009. After this quick breather, we expect the NPU market to expand in 2012 and continue growing through 2016. Increasing network traffic, which requires expansion of the access network as well as the aggregation and core networks, fuels this growth. In response, NPU vendors have opti­mized their products for specific network types, such as access versus metro.

Despite being smaller than most competitors, EZchip is the leading sup­plier of high-end merchant NPUs. The company is shipping mul­tiple product generations including the NP 4, a 100Gbps chip combining a customer-programmable NPU, traffic manager, and Ethernet MACs. EZchip has worked with Marvell to supply semicustom versions of its NPUs to Cisco. Including this Marvell revenue, sales of EZchip’s NPUs grew about 30% in 2011, much better than the overall market. For access equipment, however, the company’s NPUs are less compelling.

In the access market, PMC-Sierra is the leading active vendor. The com­pany entered the NPU market in late 2010 by acquiring Wintegra, which had become a leading vendor of access NPUs because of its flexible archi­tecture and complete data-plane software. Support for legacy protocols continues to differentiate PMC’s WinPath from Ethernet/IP-only NPUs. WinPath has been particularly successful in cost- and power-sensitive wireless-backhaul designs. In base stations, PMC was first to address both transport and RLC/MAC functions for LTE designs.

PMC’s primary competition comes from LSI, which offers its Axxia com­mu­nications processors for base-station transport and partial baseband pro­cessing as well as wireless-backhaul designs. Combining mul­tiple Power CPUs with data-plane technology from the company’s earlier APP line, the Axxia devices represent a hybrid of a multicore processor and an NPU. The company can provide unique solutions by coupling its NPUs with semicustom devices from its ASIC operations. LSI plans to extend Axxia into adjacent markets using future ARM-based processors.

With its new BCM88030, Broadcom sampled the industry’s first full-duplex 100Gbps NPU. The company combines this NPU with its 200Gbps configurable traffic manager, switch fabric, and search coprocessors to offer a packet-processing solution that is more complete than any com­petitor’s. Customers can combine these components in 400Gbps line cards or use them independently in different designs. The BCM88030 has a design win at NEC, and we expect Broadcom to increasingly challenge EZchip for new opportunities. For access and aggregation applications, Broadcom also offers configurable Carrier Ethernet switch chips in its popular StrataXGS line.

Like Broadcom, Marvell competes against EZchip for high-end NPU designs. In 1Q12, Marvell increased its emphasis on the NPU market with the acquisition of Xelerated. The company’s flagship NPU, the HX, can support 100Gbps line cards as well as standalone pizza-box configura­tions. The NP-4 and HX family offer similar throughput and integration, but EZchip’s architecture offers greater flexibility, whereas Marvell’s offers greater determinism.

Netronome is now the only privately held company developing NPU silicon. It started to generate NPU revenue in 2011 with shipments of its 40Gbps NFP-3240. Although this device cannot match the throughput of other high-end NPUs, it is unique in its ability to perform advanced services such as IPSec, firewall/NAT, load-balancing, and DPI. In 2012, Netronome disclosed its next-generation NPU—the NFP-6xxx—which should close the performance gap relative to other high-end NPUs. The NFP-6xxx, however, will lag the leaders in sampling by more than a year. The other startup offering NPU technology is Ethernity, which develops its packet processors in FPGAs.

Cisco and other leading OEMs combine search coprocessors with their internal ASIC or NPU designs. Because IPv6 and software-defined net­works (SDNs) require more-complex and larger lookups, we expect the search-coprocessor market to grow faster than the carrier-equipment market. Through its NetLogic acquisition, Broadcom becomes the leading supplier of search coprocessors. Its primary competition, Renesas, lags in technol­ogy and market share. By offering its new Neuron Search product, Cavium has entered the search-coprocessor market with an algorithmic implementation that promises to reduce power and cost while increasing capacity.

List of Figures
List of Tables
About the Authors
About the Publisher
Preface
Executive Summary
1 Introduction to Carrier Networks
Network Types and Topologies
Metro-Area Networks (MANs)
Wireline Access
Wireless Access
Equipment Types
Metro Platforms
Wireline Access Infrastructure
Wireless Access Infrastructure
2 Carrier-Network Technology
Network Layers and the OSI Model
Layers 3-7
Layers 1 and 2
Interaction Among Layers
Network Protocol Details
Ethernet
PPP
ATM
Multiprotocol Label Switching (MPLS)
Sonet/SDH
OTN
IP Multicasting
TDM Emulation
Timing Synchronization
Ethernet OAM and Protection Switching
HDLC and Frame Relay
Carrier Ethernet Services
Packet-Processing Pipeline
Control and Data Planes
Parsing
Classification
Forwarding
Modification
Network Paths and Quality of Service
Traffic Management
Policing and Shaping
Congestion Management
Scheduling
Hierarchical Traffic Management
Network and I/O Interfaces
MII, XAUI, and Derivatives
Interlaken and Interlaken Look-Aside
Utopia, POS-PHY, SPI
PCI
NPF LA‑1
Chassis and Board Standards
3 Network Processors and Search Coprocessors
What Is a Network Processor?
What Is Not a Network Processor
NPU Common Characteristics
Microarchitecture Variations
Encryption Engines
Fixed-Function Versus Programmable
Network Interfaces
Memory Interfaces
Host Interface
Software Considerations
Vendor Programming Versus Customer Programming
Search Coprocessors
What Is a Search Coprocessor?
Applications
Architecture and Common Characteristics
4 Market Size and Trends
Merchant-NPU Market Size and Segmentation
NPU Market Share by Vendor
NPU Market Forecast
Search-Coprocessor Market Share and Forecast
Market and Technology Trends
Application-Specific Specialization
3G and 4G Wireless Backhaul
OEM-Proprietary NPUs
Search-Coprocessor Trends
Multicore Processors Versus NPUs
FPGAs Versus NPUs
5 Broadcom
Company Background
Key Features and Performance
Packet Processors
Search Coprocessors
Design Details
Packet Processors
Search Coprocessors
System Design
Development Tools
Product Roadmap
Conclusions
6 EZchip
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
Conclusions
7 LSI
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
Conclusions
8 Marvell
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
Conclusions
9 Netronome
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
Conclusions
10 PMC-Sierra
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Conclusions
11 Other Vendors
Cavium
Company Background
Key Features and Performance
Conclusions
Renesas
Ethernity
Company Background
Key Features and Performance
Design Details
Conclusions
12 Legacy Vendors
AppliedMicro
Company Background
TPX Products
Legacy NPUs
Conclusions
Exar
Intel
Mindspeed
Vitesse
13 Comparing NPUs
20Gbps-and-Below NPUs
Key Differentiators
100Gbps-and-Above NPUs
Key Differentiators
14 Conclusions
NPU Vendor Outlook
EZchip
PMC-Sierra
LSI
Broadcom
Marvell
Netronome
Closing Thoughts
Appendix: Further Reading
Index
Figure 1‑1. Generic network architecture.
Figure 1‑2. Wireline access networks.
Figure 1‑3. 3GPP Release 8 LTE network architecture.
Figure 2‑1. OSI layer traversal example.
Figure 2‑2. ATM protocol stack.
Figure 2‑3. MPLS encapsulation.
Figure 2‑4. VPLS switch conceptual model.
Figure 2‑5. Control and data planes.
Figure 2‑6. Hierarchical traffic-management example.
Figure 2‑7. Standard line-card interfaces.
Figure 3‑1. Block diagram of a typical NPU.
Figure 3‑2. Hybrid search-engine architecture.
Figure 4‑1. NPU revenue by application segment, 2011.
Figure 4‑2. NPU market share by revenue, 2011.
Figure 4‑3. NPU market forecast, 2011-2016.
Figure 4‑4. Search-coprocessor market forecast, 2011-2016.
Figure 5‑1. Block diagram of Broadcom BCM88030 NPU.
Figure 5‑2. Block diagram of Broadcom BCM88650 processor.
Figure 5‑3. Block diagram of Broadcom NL5664x knowledge-based processor.
Figure 5‑4. Block diagram of a Broadcom 400Gbps line-card design.
Figure 6‑1. EZchip NP‑5 block diagram.
Figure 6‑2. 100GbE line card using EZchip NP-5.
Figure 6‑3. EZchip GPON OLT line card using NPA-3.
Figure 7‑1. LSI AXM2502-6 block diagram.
Figure 7‑2. LSI multistandard base-station design.
Figure 7‑3. LSI cell-site router design.
Figure 8‑1. Marvell HX/AX PISC architecture.
Figure 8‑2. Simplified block diagram of Marvell HX336.
Figure 8‑3. Marvell 100GbE line card.
Figure 9‑1. Conceptual block diagram of Netronome NFP-6xxx.
Figure 9‑2. Netronome NFP-6xxx 100GbE line card.
Figure 10‑1. PMC-Sierra WinPath3 block diagram.
Figure 10‑2. Wireless-backhaul aggregator based on WinPath3 and UFE4.
Figure 10‑3. Microwave backhaul using WinPath3.
Figure 11‑1. Block diagram of ENET3000 in a cell-tower gateway.
Table 2‑1. OSI reference model.
Table 2‑2. Bandwidths of common interfaces.
Table 2‑3. ITU-T standards for ATM adaptation layers.
Table 4‑1. Worldwide revenue of the top eight vendors of network processors.
Table 4‑2. Worldwide revenue of the top two vendors of search coprocessors.
Table 5‑1. Key parameters for Broadcom NPU and TM devices.
Table 5‑2. Key parameters for Broadcom KBP devices.
Table 6‑1. Key parameters for EZchip NPUs.
Table 7‑1. Key parameters for LSI Axxia devices.
Table 8‑1. Key parameters for selected Marvell NPUs.
Table 9‑1. Key parameters for Netronome NFP-3240 and NFP-6xxx.
Table 10‑1. Key parameters for PMC-Sierra WinPath devices.
Table 10‑2. WinPath protocol and interworking support.
Table 11‑1. Key parameters for Ethernity ENET devices.
Table 12‑1. Legacy-NPU vendors and status.
Table 12‑2. Key parameters for AppliedMicro TPX devices.
Table 12‑3. Key parameters for selected AppliedMicro nP devices.
Table 12‑4. Key parameters for Exar 5NP4G device.
Table 12‑5. Key parameters for Mindspeed TSP3 family.
Table 13‑1. Comparison of 20Gbps-and-below NPUs.
Table 13‑2. Comparison of 100-200Gbps NPUs.

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