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A Guide to Network Processors

14th Edition

Published October 2013

Authors: Bob Wheeler and Jag Bolaria

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Pages: Approx. 160

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The Definitive Report on Network Processing

NPUs have become a critical ingredient of carrier-equipment designs. These chips are appearing in new designs from leading OEMs spanning many applications from wireless backhaul to Carrier-Ethernet switch/routers. This broad adoption has created a merchant market that exceeded $350 million in 2012, large enough to sustain multiple vendors. Following years of market growth and vendor consolidation, only a single NPU startup remains, while all other active vendors are public companies.

Access infrastructure is migrating to Ethernet and IP backhaul while data rates for both wireline and wireless networks continue to climb. These factors are driving the need for new access NPUs with throughputs of 10Gbps or more. Meanwhile, metro-class NPUs are scaling to 200Gbps and beyond to support high-density line cards and 40G/100G Ethernet. A "Guide to Network Processors" provides a single comprehensive report covering NPUs spanning data rates from 10Gbps to 400Gbps.

This report covers customer-programmable NPUs for access and Carrier Ethernet designs, including: Broadcom’s XGS Core and Dune lines, LSI’s Axxia line, PMC-Sierra's (Wintegra) WinPath, EZchip's NPA and NPS lines, Netronome's NFP (Intel IXP derivative), and Marvell's Xelerated HX and AX lines. This report also includes coverage of search coprocessors, such as Broadcom’s (NetLogic’s) KBP products, which are often used with high-end NPUs.

Only The Linley Group follows this market closely enough to give you the complete picture. Which vendors are in this business for the long haul? How do the latest products stack up? What is the market outlook for merchant NPUs? "A Guide to Network Processors" is the result of years of research that cannot be duplicated. If you are interested in following this strategic standard-product segment, you have located the definitive source.

Get Facts, Not Fiction

This report cuts through the vendor hype and gives you the solid information you need to understand this market. "A Guide to Network Processors" analyzes each vendor and each product, probes their strengths and weaknesses, then presents key details in a consistent, easy to compare fashion. For those less familiar with this combination of networking and CPU design, the report includes several introductory chapters that define and describe basic concepts and key technologies.

The Linley Group is the most recognized and respected name for technology and market analysis of network processors. Don't be fooled by weak overviews written by market analysts who really don't understand how a network processor works. The "Guide" provides a unique combination of business and technology savvy from the leading analysts in this market. Bob Wheeler and Jag Bolaria use their long experience in the networking world to analyze these devices. Together, the two authors ignore the fiction and provide the real story on each NPU vendor and its products.

Don't miss the latest information on this important market. Order now.

This report is written for:

  • Engineers who are designing networking equipment and need to select a network processor (NPU)
  • Marketing and engineering staff at companies that sell NPU products who desire competitive information
  • Technology professionals who want an introduction to networking and network processors
  • Financial analysts who desire a detailed analysis and comparison of NPU companies and their chances of success
  • Network architects at carriers and service providers who need to get up to speed on this technology

What's New in This Edition

Updates to the 14th Edition of "A Guide to Network Processors"

A Guide to Network Processors" has been extensively updated to include the latest disclosures from NPU vendors as well as 2012 market data.

Here are some of the many changes you will find:

  • New quantitative market data, including:
    • NPU-vendor market shares for 2012
    • Search coprocessor vendor market shares for 2012
    • NPU market segmentation by application
    • Forecasts for merchant NPUs and search coprocessors through 2017
  • Coverage of EZchip’s new NPS-400 NPU/TM.
  • Coverage of LSI's PMC's new Axxia AXM2500WinPath4.
  • Coverage of Netronome's Broadcom's new NFP-6xxx 200Gbps NPUNLA12000 KBP.
  • New Marvell chapter incorporating the former-Xelerated NPUs.
  • New Cavium XeL Technology section covering the company's algorithmic search coprocessors.
  • Extensive updates to company-background information, roadmaps, and analysis for major NPU vendors.
  • Revised and updated tutorials.

All Tier One networking and communications OEMs use NPUs in a range of systems, including edge/services routers, Carrier Ethernet switch/ routers (CESRs), optical-transport platforms, and wire¬less and broad¬band infrastructure. Many of these OEMs continue to invest in internal NPUs, which limit the adoption of merchant products. But most of those with internally developed NPUs still use merchant NPUs in some designs.

Because semiconductors are subject to occasional inventory corrections, the merchant-NPU market has dis¬played a somewhat volatile growth rate over the past decade. This trend continued through the recession of 2009, followed by an upswing in 2010. What followed, however, was an un¬pre-cedented two-year decline in 2011–2012. This decline was due to several factors including inventory correc¬tions, weak macroeconomic conditions, and declining revenue from ancillary markets. But the merchant-NPU market was still about $100 million larger in 2012 than it was in 2007, and we predict it will reach nearly half a billion dollars in 2017.

Despite being smaller than most competitors, EZchip is the leading sup-plier of high-end merchant NPUs. The company is shipping mul¬tiple product generations including the 100Gbps NP-4. EZchip is also sampling the NP-5, the industry's first 200Gbps chip combining a customer-programmable packet processor, traffic manager, and Ethernet MACs. It has worked with Marvell to supply special versions of its NPUs to Cisco, which primarily uses them in the ASR 9000 router. EZchip is developing a new line of NPUs, called NPS, that handle Layer 4–7 features and promise easier programming than traditional NPUs.

In the access market, PMC-Sierra is the leading vendor. The company entered the NPU market in late 2010 by acquiring Wintegra, which had become a leading vendor of access NPUs because of its flexible archi-tecture and complete data-plane software. Since the acquisition, PMC has increasingly focused on wireless-backhaul designs, where support for legacy protocols continues to differentiate the WinPath NPUs from Ethernet/IP-only NPUs. Secondary markets for WinPath include wireless base stations and broadband-aggregation equipment. In 2013, PMC is sampling WinPath4, which scales performance to 40Gbps.

With its BCM88030, Broadcom is shipping the industry's first full-duplex 100Gbps NPU. The company combines this NPU with its 200Gbps configurable traffic manager, switch fabric, and search coprocessors to offer a packet-processing solution that is more complete than any com-petitor's. Customers can combine these components in 400Gbps line cards or use them independently in different designs. Broadcom also provides ASIC services to OEMs wishing to develop in-house NPUs, such as Alcatel-Lucent with its FP3. For access and aggregation applications, it instead offers configurable Carrier Ethernet switch chips in its popular StrataXGS line.

In addition to its manufacturing role with EZchip, Marvell supplies high-end NPUs of its own design. These products come from the company's acquisition of NPU startup Xelerated. The company's flagship NPU, the HX, can support 100Gbps line cards as well as standalone pizza-box configura¬tions. The derivative AX line delivers programmable packet processing for access- and aggregation-switch designs. Marvell has also added traffic-management technology from its NPUs to configurable Carrier Ethernet switch chips, which address lower-cost access designs.

LSI is an incumbent vendor of access NPUs but has taken a new direction with its Axxia com¬mu¬nications processors. Combining mul¬tiple general-purpose CPUs with data-plane technology from the company's earlier APP line, the Axxia devices represent a hybrid of a multicore processor and an NPU. Rather than targeting NPU applications, however, Axxia pri¬marily targets wireless base stations. Through its ASIC operations, LSI offers semicustom devices that can integrate baseband pro¬cessing.
Netronome is now the only privately held company developing NPU sili-con. It started to generate NPU revenue in 2011 with initial shipments of its 40Gbps NFP-3240. Although this device cannot match the throughput of high-end NPUs, it is unique in its ability to perform advanced services such as IPSec, SSL, firewall/NAT, load balancing, and deep packet inspection (DPI). Rather than competing for carrier designs, Netronome principally targets security appliances and other data-center applications. In 2014, Netronome plans to sample the NFP-6xxx, its next-generation NPU that will scale throughput to 200Gbps.

Also referred to as TCAMs or network search engines (NSEs), search coprocessors offload NPUs by performing lookup functions. Cisco and other leading OEMs combine search coprocessors with both merchant and internal NPUs, resulting in a merchant search-coprocessor market about two-thirds the size of the merchant-NPU market. As with NPUs, some OEMs also possess proprietary search designs.
Through its NetLogic acquisition, Broadcom became the dominant sup-plier of search coprocessors, which the company calls knowledge-based processors (KBPs). Its traditional competitor, Renesas, has fallen behind in technol¬ogy and is losing market share. Two new entrants, Cavium and XeL Technology, hope to compete with Broadcom using algorithmic implementations that promise to reduce power and cost. By 2015, OEMs should have several competitive vendors to choose from.

List of Figures
List of Tables
About the Authors
About the Publisher
Executive Summary
1 Introduction to Carrier Networks
Network Types and Topologies
Metro-Area Networks (MANs)
Wireline Access
Wireless Access
Equipment Types
Metro Platforms
Wireline Access Infrastructure
Wireless Access Infrastructure
2 Carrier-Network Technology
Network Layers and the OSI Model
Layers 37
Layers 1 and 2
Interaction Among Layers
Network Protocol Details
Multiprotocol Label Switching (MPLS)
IP Multicasting
TDM Emulation
Timing Synchronization
Ethernet OAM and Protection Switching
HDLC and Frame Relay
Carrier Ethernet Services
Packet-Processing Pipeline
Control and Data Planes
Network Paths and Quality of Service
Traffic Management
Policing and Shaping
Congestion Management
Hierarchical Traffic Management
Network and I/O Interfaces
MII, XAUI, and Derivatives
Interlaken and Interlaken Look-Aside
Utopia, POS-PHY, SPI
PCI Express
Chassis and Board Standards
3 Network Processors and Search Coprocessors
What Is a Network Processor?
What Is Not a Network Processor
NPU Common Characteristics
Microarchitecture Variations
Encryption Engines
Fixed-Function Versus Programmable
Network Interfaces
Memory Interfaces
Host Interface
Software Considerations
Vendor Programming Versus Customer Programming
Search Coprocessors
What Is a Search Coprocessor?
Architecture and Common Characteristics
4 Market Size and Trends
Merchant-NPU Market Size and Segmentation
NPU Market Share by Vendor
NPU Market Forecast
Search-Coprocessor Market
Technology Trends
OEM-Proprietary NPUs
Alcatel-Lucent FlexPath
Cisco QuantumFlow Processor and nPower X1
Ericsson SNP-4000
Huawei Solar
Juniper Junos Trio
NPU Technology Trends
Application-Specific Specialization
3G and 4G Wireless Backhaul
Multicore Processors Versus NPUs
FPGAs Versus NPUs
5 Broadcom
Company Background
Key Features and Performance
Packet Processors
Search Coprocessors
Design Details
Packet Processors
Search Coprocessors
System Design
Development Tools
Product Roadmap
6 EZchip
Company Background
Key Features and Performance
Internal Architecture
NP and NPA
System Design
Development Tools
Product Roadmap
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
8 Marvell
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
9 Netronome
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
Product Roadmap
10 PMC-Sierra
Company Background
Key Features and Performance
Internal Architecture
System Design
Development Tools
11 Search-Coprocessor Vendors
Company Background
Key Features and Performance
XeL Technology
Company Background
Key Features and Performance
12 Legacy Vendors
13 Comparing NPUs
50Gbps-and-Below NPUs
Key Differentiators
100Gbps-and-Above NPUs
Key Differentiators
14 Conclusions
NPU-Vendor Outlook
Closing Thoughts
Appendix: Further Reading
Figure 1‑1. Generic network architecture.
Figure 1‑2. Wireline access networks.
Figure 1‑3. 3GPP Release 8 LTE network architecture.
Figure 2‑1. OSI layer traversal example.
Figure 2‑2. ATM protocol stack.
Figure 2‑3. MPLS encapsulation.
Figure 2‑4. VPLS switch conceptual model.
Figure 2‑5. Control and data planes.
Figure 2‑6. Hierarchical traffic-management example.
Figure 2‑7. Standard line-card interfaces.
Figure 3‑1. Block diagram of a typical NPU.
Figure 3‑2. Hybrid search-engine architecture.
Figure 4‑1. NPU revenue by application segment, 2012.
Figure 4‑2. Merchant NPU market share by revenue, 2012.
Figure 4‑3. Merchant NPU market forecast, 20122017.
Figure 4‑4. Search-coprocessor market forecast, 20122017.
Figure 5‑1. Block diagram of Broadcom BCM88030 NPU.
Figure 5‑2. Block diagram of Broadcom BCM88650 processors.
Figure 5-3. Block diagram of Broadcom NLA12k KBP.
Figure 5‑4. Block diagram of a Broadcom-based 400Gbps line card.
Figure 6‑1. Block diagram of EZchip NP‑5.
Figure 6‑2. Block diagram of NPS network-processing cluster (NPC).
Figure 6‑3. Block diagram of EZchip NPS‑400.
Figure 6‑4. 100GbE line card using EZchip NP-5.
Figure 7‑1. Block diagram of LSI AXM2502-5.
Figure 7‑2. LSI multistandard base-station design.
Figure 7‑3. LSI cell-site router design.
Figure 8‑1. Marvell HX/AX PISC architecture.
Figure 8‑2. Simplified block diagram of Marvell HX336.
Figure 8‑3. Marvell 100GbE line card.
Figure 9‑1. Conceptual block diagram of Netronome NFP-6xxx processor.
Figure 9‑2. Netronome NFP-6xxx appliance.
Figure 10‑1. Block diagram of PMC-Sierra WinPath4.
Figure 10‑2. Wireless-backhaul aggregator based on WinPath4 and UFE4.
Figure 10‑3. Microwave backhaul using WinPath3.
Table 2‑1. OSI reference model.
Table 2‑2. Bandwidths of common interfaces.
Table 2‑3. ITU-T standards for ATM adaptation layers.
Table 4‑1. Worldwide revenue of the top six vendors of network processors.
Table 4‑2. Worldwide revenue of the top two vendors of search coprocessors.
Table 5‑1. Key parameters for Broadcom NPU and TM devices.
Table 5‑2. Key parameters for Broadcom KBP devices.
Table 6‑1. Key parameters for EZchip NPUs.
Table 7‑1. Key parameters for LSI Axxia devices.
Table 8‑1. Key parameters for selected Marvell NPUs.
Table 9‑1. Key parameters for Netronome NFP-3240 and NFP-6xxx.
Table 10‑1. Key parameters for PMC-Sierra WinPath devices.
Table 10‑2. WinPath protocol and interworking support.
Table 11‑1. Key parameters for XeL ISE and ISP search coprocessors.
Table 12‑1. Legacy-NPU vendors and status.
Table 12‑2. Key parameters for selected AppliedMicro nP devices.
Table 13‑1. Comparison of 4050Gbps NPUs.
Table 13‑2. Comparison of 100200Gbps NPUs.


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