Processor Conference 2013
Conference Proceedings Available Now
Held on October 16 - 17, 2013

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Agenda for Day Two: Thursday October 17, 2013
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9:00am-10:35amSession 6: High-Performance Packet Processing

The high data rates in next-generation networking equipment demand application-specific solutions. This session, moderated by senior analyst Bob Wheeler, explores innovative technologies that can customize your system design for optimal throughput.

Overcoming Security Protocol Bottlenecks at 40 Gbps and Beyond
Bart Stevens, VP Silicon IP and Secure Protocols Business Line, Verimatrix

Multicore processors must accelerate security protocols at line rates approaching 40Gbps (and soon beyond). Common protocols include MACsec, IPsec, SSL, TLS, and DTLS. Implementing these crypto algorithms at 40Gbps will severely tax a CPU. Intelligent protocol-aware packet processing ensures efficient data movement in and out of cores, managing buffers and multiple simultaneous data paths to mitigate high memory latency and overcome system bottlenecks. This presentation will provide examples of security packet-engine IP that enables high throughput.

Hyper-Efficient Processing for the New Mobile Internet
Martin White, Senior Principal Architect, Marvell

With the explosive growth of data traffic and devices driven by the Mobile Internet and the Internet of Things, the carrier infrastructure network is undergoing a major transformation to support terabit capacities, IPv6 scaling, adaptive service flexibilities, enhanced security and exceptional quality of experience. The next-generation converged intelligent network requires hyper-efficient programmable packet processing technologies in order to meet these challenges. This presentation will show how Marvell solves these requirements with its network processing and traffic-management solutions.

Enabling Data Path Services via Multidimensional Programmable Solutions
Mark Gustlin, Principal System Architect, Xilinx

Next-generation line cards require power-to-performance optimized solutions and unified data-path services that scale to multi-hundred gigabits-per-second. This presentation describes a unified packet-processing solution that features an FPGA directly in the data path. Based on Xilinx SmartCORE IP, this solution encompasses packet parsing, integrated search and packet editing, and hierarchical traffic management.

Implementing Deep Packet Inspection using OpenCL Channels
Nick Finamore, Market Development Manager, Computer and Storage BU, Altera now part of Intel

Unlike CPUs and GPUs, FPGAs provide an incredibly rich set of high bandwidth and configurable IOs. The data from these IOs can be processed directly by the FPGA fabric to enable high-performance streaming applications. Altera has extended the OpenCL standard with a vendor extension called channels which allows streaming applications to be described completely in software. This ability is extremely important for describing and implementing network and communications applications using FPGAs. This presentation will show how OpenCL can express a Deep Packet Inspection (DPI) application and provide results of the implementation that was automatically generated from Altera's SDK.

Q&A and panel discussion featuring the above speakers.

10:35am-10:55amBreak - Sponsored by Synopsys
10:55am-12:00pmSession 7: Licensable CPU Cores for Networking SoCs

Networking chips cover of range of price and performance points, so one size CPU does not fit all applications. This session, moderated by senior analyst Kevin Krewell, discloses two new families of licensable CPUs that will power next-generation chip designs.

Enter the ‘Warrior’
Mark Throndson, Director of Processor Technology Marketing, Imagination

Imagination's next-generation MIPS Series5 family of CPU IP cores, code-named Warrior, will include advanced architectural features such as virtualization, SIMD and hardware multi-threading plus true 32/64-bit capability across the range, delivering high performance, low power and silicon utilization. In this presentation, we'll unveil the first of the 'Warrior' cores, including key features and performance data, and give more insight into what is coming next.

Introducing a Power-Efficient Processor Family for Communications and IOT
Charlie Hong-Men Su, CTO, SVP of R&D and Cofounder, Andes Technology

Balancing performance against power in new applications continues to be a challenge for SOC designers. Whether the application is communications, networking, or even IOT (Internet of Things), optimal application performance for the power budget is critical. The AndeStar V3 architecture provides a flexible foundation to implement a wide range of performance-efficient processors. This presentation will introduce a core with flexible data-engine support to accelerate the heavy duty connectivity/networking layer, a power-efficient 1 GHz+ CPU to serve application-layer devices and a new compact CPU core with built-in flash support to serve the cost- and power-conscious sensing nodes.

Q&A and panel discussion featuring the above speakers.

12:00pm-1:15pmLunch - Sponsored by Applied Micro Circuits
1:15pm-2:20pmSession 8: Processors for the Evolving Data Center

Data centers are the fastest-growing networking market. This session, moderated by principal analyst Linley Gwennap, examines how the needs of the data center are changing and how the newest processors address these needs.

Network and Compute Convergence
Michael Zimmerman, VP of Marketing, Tilera

Security and networking workloads and Software Defined Networking (SDN) are game changers for next-generation data centers and cloud deployment. The server is evolving to handle massive packet flows representing applications, users and content. This is changing the way servers, NICs, virtualization and switches are architected and connected. In addition, NFV will accelerate the convergence of networking, security and virtualized cloud deployment. This presentation will introduce new products designed to meet the needs of the evolving high-performance data center.

X-Gene: 64-bit ARM Software Eco-system
Kumar Sankaran, Associate VP, Software and Platform Engineering, AppliedMicro

As more and more enterprise applications move to the cloud, enterprise system vendors are adopting an open architecture to deliver data and services. 64-bit ARM is a natural platform of choice, with the performance and scalability to address the entire spectrum of applications. This presentation will discuss AppliedMicro's X-Gene ARM64 platform, and how its driving the ecosystem for complete software platforms that can be deployed in the enterprise.

Q&A and panel discussion featuring the above speakers.

2:20pm-2:40pmBreak - Sponsored by Synopsys
2:40pm-4:15pmSession 9: Challenges in Implementing SDN and NFV

Software defined networking (SDN) and network function virtualization (NFV) are new tools to simplify networks, but they don't necessarily simplify the hardware. This session, moderated by senior analyst Loring Wirbel, discusses the challenges facing system designers to implement these standards, thereby demanding higher-performance processors.

Building Scalable and Efficient SDN and NFV Architectures
Sandeep Shah, Director of Systems Architecture, EZchip

The communications industry must transition to new architectures for network virtualization, Software Defined Networking (SDN) and Network Functions Virtualization (NFV). Using general purpose CPUs to run control plane and data plane is not viable for high performance applications in large carrier and data center networks. In this presentation EZchip will outline SDN and NFV architectures that utilize its new NPS network processor for placing data-plane functions where needed in a variety of hardware configurations, allowing flexible, scalable and efficient networks.

SDN Deployment Challenges and Solutions
Raghu Kondapalli, Director of Strategic Planning and Technology, LSI

SDN has moved beyond proof of concept with deployments in data center and carrier environments, but scalability challenges need to be addressed before SDN becomes pervasive. Control-plane functional coordination and distributed network-state management are complex tasks, requiring network-architecture and solution-level changes. Although SDN architecture is software-centric, function-specific hardware acceleration is key. This presentation will address several SDN deployment challenges and offer solutions including control-plane acceleration.

Building NFV Enabled Systems Using Multicore SoCs
Prasun Kapoor, Director Software Engineering, Cavium

NFV solutions require virtualization capability in compute, networking and storage systems. This presentation will outline how Network Services Processors (NSPs) have evolved to support standard virtualization technologies (virtualized cores, I/O MMU, PCIe/SR-IOV based interface to hardware acceleration engines, etc.) such that they combine the best of both compute and network processing. Telecom equipment manufacturers can use NSPs to build NFV-enabled systems that provide high-performance networking with low power while offering service providers a familiar orchestration-and-management software layer to provision and manage virtual machines and easily instantiate new services.

Q&A and panel discussion featuring the above speakers.

 

Premier Sponsor

Cavium Networks

AppliedMicro

Platinum Sponsor

Freescale

Gold Sponsor

EZchip

Broadcom

Xilinx

LSI

Micron

Tilera

ASOCS

Target

Andes Technologies

NetSpeed Systems

Industry Sponsor

EEMBC

HyperTransport Consortium

Power.org

Ethernet Alliance