Processor Conference 2015
Focused on Processors for Embedded and IoT Applications
Held On October 6 - 7, 2015

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Agenda for Day One: October 6, 2015
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Processor Technology and Market Trends
Linley Gwennap, Principal Analyst, The Linley Group

Processors continue to increase in complexity, making them more difficult to design, program, and integrate into a system. Choosing the right processor is also a challenging task. This presentation will discuss technology trends including heterogeneous computing, network function virtualization (NFV), vision processing, and changes in Moore's Law. It will also provide market share for leading processor vendors and a forecast for market growth.

9:45am-10:30amSession 1: High-Performance Processor Design

Today's processor designs are complex SoC designs combining many cores. This session, moderated by The Linley Group principal analyst Linley Gwennap, examines new ways to combine and connect these cores, including network-on-a-chip (NoC) IP and an opposing concept from Marvell to simplify the SoC. Presentations from Cadence and the HSA Foundation address heterogeneous computing and how it affects processor design.

Moving from SoC to Virtual SoC
Noam Mizrahi, Associate VP, SoC Product definition, Chief Architect, Networking, Compute BU, Marvell

Progress in chip design over the last few decades has been nothing less than amazing, considering that billions of transistors must work together seamlessly in a single, highly integrated SoC. But this complexity is finally taking its toll, causing longer, more expensive development cycles and added inefficiencies. This presentation will discuss the innovative Modular Chip virtual SoC (MoChi vSoC) approach, an alternative way to design modern complex processors, and explain how it is being deployed in Marvell's future SoC products.

Cache Coherency: Breaking Through the Limits of Configurability
Joe Rowlands, Chief Architect, NetSpeed Systems

Today's SoCs combine a multitude of on-chip CPU cores, computing clusters, and other IP blocks. But more compute elements doesn't always translate to better performance. Without a high-performance and power-efficient shared-memory communication system that is configured to match application-specific demands, the SoC will bottleneck. Configuring coherent systems requires a rare expertise. In this presentation, NetSpeed will announce new technology that uses automation and advanced algorithms to ensure correct results when configuring coherent systems.

10:30am-10:50amBreak - Sponsored by Cadence
10:50am-12:30pmSession 1: High-Performance Processor Design (cont)

Optimizing Quality-of-Service (QoS) With Interconnect and Memory Controller IP
Benoit de Lescure, Vice President, Technology, ArterisIP and Marc Greenberg, Director of Product Marketing, Synopsys

Traditional SoC design techniques optimize QoS at a local level, whereas new methods consider the complete dataflow path. This presentation examines pitfalls in optimizing QoS at the local level and recommends best practices for co-optimizing the on-chip network-on-chip (NoC) and memory controller. It also addresses trading off latency versus bandwidth, reducing system power, increasing DRAM efficiency, and implementing memory interleaving. The presentation will introduce new interfaces that enhance interconnect and memory integration.

Instruction Set Innovation in Fourth Generation Vision DSPs
Chris Rowen, CEO, Cognite Ventures

In this presentation, Cadence will unveil the architecture for its fourth generation of vision DSPs. Based on work done with customers and Cadence's own extensive research, the presentation will describe instruction-set improvements in arithmetic operation parallelism and functionality, memory system throughput, and VLIW encoding. The new architecture provides up to 9x improvement in vision processing throughput and energy efficient per core. This new architecture applies to a wide variety of applications that require increasing resolution, faster refresh rates, and scaling to tera-op throughput.

Heterogeneous Systems Architecture: Coming Soon to a Platform Near You
Jim Nicholas, Vice President MIPS Business Operations, Imagination Technologies, on behalf of the HSA Foundation

Heterogeneous processing represents the future of computing, promising to unlock the performance and power efficiency of the parallel computing engines found in most modern electronic devices. Founding members of the HSA (Heterogeneous System Architecture) Foundation will detail the HSA computing platform infrastructure including features/advantages across computing platforms from mobile and tablets to desktops to HPC and servers. Following the release of the v1.0 specification in March 2015, the presentation will discuss important new developments that are bringing the industry closer to broad adoption of heterogeneous computing.

There will be Q&A and a panel discussion featuring above speakers.

12:30pm-1:50pmLunch - Sponsored by Freescale
  Track A - IoT Track B - Data Plane
1:50pm-3:20pmSession 2: IoT Client SoCs

In client devices for the Internet of Things (IoT), processors often need to run on batteries for years, even while maintaining wireless connectivity. Developing IoT SoCs that consume little power while delivering adequate performance and cloud connectivity presents severe design challenges. This session, moderated by The Linley Group's senior analyst Loyd Case, delves into how to best balance the conflicting requirements of IoT SoCs.

Developing an Ultra Low Power Processor for IoT Applications
Frankwell Lin, President, Andes Technology

IoT devices may need to last for years on a single battery charge. Conventional techniques provide some power savings, but custom instructions to accelerate compute-intensive tasks provide greater improvements in performance and power efficiency. KNECT.ME is a multi-company initiative to promote best-in-class IP that enables designers to achieve the full measure of their IoT product specification. This presentation describes a smart solution for an IoT device including a high-performance processor core with low power and low cost (small silicon footprint).

Balancing Processor Performance and Energy Consumption for IoT Applications
Fergus Casey, Senior R&D Manager, ARC Processors, Synopsys

Many IoT applications operate from small batteries but are continually evolving to add features and functions, challenging designers to balance energy consumption and performance. Often the system architect wants application-processor performance while maintaining the power of an 8-bit microcontroller. Flexible and configurable processor architectures enable designers to meet performance demands without sacrificing energy efficiency. This session presents techniques and options to reduce system power through processor IP selection and configuration.

Easy Prototyping Gets IoT Devices to Market Faster
Steven Si, Technical Director, MediaTek

The IoT market is developing at a rapid pace. New features and capabilities, even entirely new product categories are emerging on an almost daily basis. Developers must race to get their ideas to market before the competition. Prototyping a new IoT product can be a major bottleneck in the development process, however. This presentation will discuss how MediaTek's LinkIt platform, powered by IoT-optimized SoCs such as the MT2502 and MT7681, can simplify the prototyping process, speeding time to market.

There will be Q&A and a panel discussion featuring above speakers.

Session 4: Network Security

Public and private data centers must provide secure connectivity and secure sessions. To support high data rates, custom hardware is needed, but this hardware must handle a wide range of cryptographic and security algorithms. This session, moderated by The Linley Group principal analyst Jag Bolaria, discusses the challenges in delivering SoCs that are fast, flexible, and secure

Challenges of Multi Gigabit Security Protocol Acceleration in SoCs
Steve Singer, Senior Director, WW Field Applications Engineering, Rambus

Security has become an absolute must in today's networks. In wired networks, protocols such as MACsec, IPsec, SSL/TLS, DTLS, and sRTP (VoIP) enable data security and authentication at various layers of the network. On the wireless front, LTE infrastructure equipment requires stringent security at high performance and low power. This presentation will explore dedicated crypto and security-protocol acceleration for enabling end-to-end network security. It will also show power and performance tradeoffs between hardware and software implementations.

Crypto and Compliance Solutions for the Cloud
Tejinder Singh, Associate Director Accelerator & Adapter Group, Cavium

Crypto performance requirements for cloud and traditional data centers are increasing exponentially, and new crypto algorithms (symmetric and asymmetric) continue to emerge. Private-key security in the public cloud is becoming a challenge for IaaS users. Applications that require FIPS 140-2 security and are moving to the cloud need a FIPS 140-2 solution architected for the cloud. Cavium's Nitrox processors and LiquidSecurity appliances address these requirements for cloud and enterprise usage models.

GPU-Based IPSec Acceleration for Flexible Networks
Seong Kim, System Architect, AMD

Service providers are looking to increase service agility and flexibility to reduce total cost of ownership for next generation networks. GPU acceleration is an effective option to lower cost and power. Most importantly it can provide flexibility compared with hard coded accelerators. This presentation will cover AMD GPU based IPsec acceleration for NFV applications detailing how the GPU is used to accelerate IPsec and related performance, power, and flexibility benefits.

There will be Q&A and a panel discussion featuring above speakers.

3:20pm-3:40pmBreak - Sponsored by Cadence
3:40pm-5:10pmSession 3: Secure IoT Gateways

Security must become more than an afterthought when designing chips and devices for the Internet of Things (IoT). The more personalized the device, the more personalized the information it can collect -- and leak. This session, moderated by The Linley Group's senior analyst Tom Halfhill, covers various aspects of IoT security in chip-level hardware and system software.

Secure IoT Gateways
Matt Short, Senior Product Manager, Freescale

Security challenges continue to increase as a more personal, available, and portable IoT rolls out – beginning at the edge. As users become concerned about their digital footprint, this new intelligent edge will be the front line of defense. This presentation will review the implementation of ARM cores in a comprehensive SoC targeted at the intelligent edge, exploring the tradeoffs between running applications on general-purpose cores, when/where to apply dedicated offload technology, and how to develop a flexible data path that provides ease of software development.

Technologies for Securing NFV or IoT Systems in Embedded Linux
Iisko Lappalainen, Senior Manager, Technical Pre-Sales and Solutions, Cavium

This presentation will cover solutions using a hardware-assisted root-of-trust to build security through the bootloader, Linux kernel and GNU/Linux user space. It will also review the use of Mandatory Access Control to reach Common Criteria EAL security levels for the target products. Finally, it will present use-cases and applications of the technology in the NFV and IoT markets.

Connected, Heterogeneous and Ubiquitous: Securing SoCs in the IoT Era
John Min, Director of Processor Technology Marketing, Imagination

Evolving use models, device interconnectedness, and heterogeneous computing models are driving the need for a new security paradigm in next-generation SoCs. In the IoT, connected edge devices will need more powerful local processing. Security challenges increase through the introduction of new OSes and connectivity engines, leading to a larger attack surface area. This presentation will discuss implementation of hardware separation-based security across all the processors in a heterogeneous embedded device, enabling IoT products that are trusted and robust.

There will be Q&A and a panel discussion featuring above speakers.

Session 5: High-Speed Packet Processing

Carriers are now deploying network function virtualization (NFV), and data centers are poised to adopt 100G Ethernet next year. These trends are driving new architectures for packet processing and network memories. This session, moderated by The Linley Group's principal analyst Bob Wheeler, explores innovative technologies that can deliver the required combination of throughput and flexibility.

An Optimized Processing Architecture for NFV Application Workloads
Daniel Proch, Director of Product Management, Netronome

Traditionally, custom hardware and software were needed to meet the stringent performance requirements of networking and security applications. NFV is intended to change that by combining off-the-shelf components for application processing with optional acceleration. NFV platforms use OVS to interconnect the network and virtual network functions. This presentation will compare various application workloads and performance in accelerated/non-accelerated configurations to show how a new class of intelligent NICs can improve performance by returning CPU cores to the applications and services that need them.

Use Cases for the NPS – a C-Programmable 7-Layer Network Processor
Sandeep Shah, Director of Systems Architecture, EZchip

EZchip will sample later this year a 400Gbps NPU that combines C programmability, Linux operating system, processing of all seven network layers, stateful flow tracking, and hardware accelerators. The NPS chip enables a broad range of networking applications, beyond the L2-3 processing and routing applications that have traditionally been identified with NPUs. This presentation will showcase a great diversity of use cases for this processor in carrier, data center, and enterprise networks.

Bandwidth Engine 3 Accelerates Scalable SDN Flow Rates and Awareness
Michael J Miller, VP of Technology Innovation and System Applications, MoSys

The third-generation Bandwidth Engine has been architected for high access rate, throughput and intelligent offload for network processing. In this talk, MoSys will disclose the initial offerings, including a device optimized for the EZchip NPS-400 used in intelligent white box solutions for carrier and data center applications where traffic management and flow awareness are important. The addition of BE-3 to NPS-400 seamlessly increases the packet processing rate by delivering higher lookup bandwidth, while optimizing the overall power efficiency and improving performance density.

There will be Q&A and a panel discussion featuring above speakers.

5:10pm-6:40pmReception - Sponsored by Synopsys


Platinum Sponsor


Cavium Networks

Gold Sponsor


NetSpeed Systems

Andes Technologies


AMD logo

New Soft Machines logo

Industry Sponsor


Linaro Industry