Linley Data Center Conference 2016
Covers system design for data-center servers and networking
Held on February 9 - 10, 2016
Hyatt Regency Hotel, Santa Clara, CA

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Agenda for Day One: Tuesday February 9, 2016
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The Silicon Foundation of Cloud Computing
Bob Wheeler, Principal Analyst and Jag Bolaria, The Linley Group

In this keynote, The Linley Group analysts provide insights into the important trends driving silicon for servers and networking, including process technology, workload acceleration, SDN/NFV, and vendor consolidation. We examine how these trends impact the chips sitting at the heart of data-center equipment. We also provide a high-level view of the chip-vendor landscape, which remains surprisingly dynamic.

There will be time for Q&A following the presentation.

10:00am-10:20amBREAK – Sponsored by NXP
10:20am-11:50amSession 1: Implementing SDN & NFV

This session, moderated by Bob Wheeler, Principal Analyst at The Linley Group, will focus on architecture and implementation for software-defined networking (SDN) and network functions virtualization (NFV).

Smart ToR Switch and Scale-Out Router Architectures for Data-Center Networks
Sandeep Shah, Director of Systems Architecture, EZchip

SDN and NFV open powerful opportunities for network operators. Switches and routers can now evolve to new architectures that utilize intelligent ToR switches and scale-out routers to realize tremendous benefits, in particular seamless scalability, services agility, and dramatically reduced CAPEX and OPEX. In this session EZchip will present system and network architectures utilizing readily available hardware and software components and leveraging its new NPS network processor, that enable powerful SDN and NFV networks that are fully programmable, flexible and high-performance.

Comparison of Open vSwitch Implementation Options
Nick Tausanovitch, Vice President of Solutions Architecture and Silicon Product Management, Netronome

The benefits of OVS for host-based networking deployments are well established, such as software-defined flexibility and control of data path functions for fast feature rollouts. Yet challenges remain to implement these functions with acceptable performance and CPU burdens. We discuss various OVS implementation approaches and provide benchmarks for packet throughput and CPU utilization for common use cases in virtualized server environments. Tradeoffs regarding performance, scalability, flexibility, and cost are discussed in a holistic way, concluding with observations on best practices.

Hardware-Agnostic VNF Acceleration
John Myla, Principal Software Engineer, NXP

Network Function Virtualization Infrastructure (NFVI) enables Virtual Network Functions (VNFs) to run as software-only entities in a hardware agnostic fashion. Since compute intensive (CI) operations of VNFs consume CPU cycles, achieving high performance for CI applications is a challenge. In this session, John will discuss how to achieve higher performance of VNFs by offloading using vendor-specific interfaces to hardware accelerators. In addition, he will cover how standard vendor-independent "Virtual Accelerator Interfaces" are essential to achieving hardware-agnostic VNF acceleration.

There will be Q&A and a panel discussion featuring above speakers.

1:00pm-2:30pmSession 2: Architectures for Workload Acceleration

This session, moderated by Jag Bolaria, Principal Analyst at The Linley Group, will discuss how various cloud workloads may be accelerated using programmable or optimized silicon.

FPGA Acceleration in Data-Center Applications
Alex Grbic, VP, Product Marketing and Planning, Programmable Solutions Group, Altera now part of Intel

New FPGAs are expected to deliver 10X improvements in performance over the previous two FPGA generations for some key data-center workloads. FPGA architectures deliver flexible accelerators for cloud data centers and enable significant data reuse for workloads such as neural networking, which improves power efficiency and lowers external memory bandwidth requirements. This presentation will showcase recent breakthroughs in FPGA architectures and the corresponding benefits to managing data-center workloads.

High-Speed I/O Processor Accelerates Data-Center Software Defined Infrastructure
Jean-Pierre Demange, Vice President, Marketing, Kalray

Software defined infrastructure (SDI) is reshaping datacenters, starting with networking and storage. ASICs and FPGAs are not flexible enough to keep up with the requirements of these rapidly changing ecosystems. The Kalray MPPA2-256 High Speed I/O Processor provides a breakthrough solution for these new requirements. Its unique architecture, based on 256 fully C/C++ programmable cores, tightly integrated with high-speed IOs, delivers unmatched low power, low latency, real-time performance, resulting in an industry leading solution for software-defined networking and storage.

Emerging User-Space Crypto APIs
Geoff Waters, Senior Principal Engineer – Security, Digital Networking, NXP

In the increasingly virtualized world of data-center and edge computing, application mobility will be critical. To facilitate mobility without sacrificing security or performance, computationally intensive encryption functions will still need to be accelerated in hardware, but the hardware must be properly abstracted. In this session, Geoff will discuss emerging API standards for crypto acceleration.

There will be Q&A and a panel discussion featuring above speakers.

2:30pm-2:50pmBREAK – Sponsored by NXP
2:50pm-3:50pmSession 3: High-Speed Ethernet Interconnects

This session moderated by Loring Wirbel, Senior Analyst at The Linley Group, will examine the newest Ethernet technologies for data-center networks along with physical-layer implementations.

PAM Interconnects: The Future of Optical Cloud Data Centers
Scott Feller, Associate VP of Product Marketing, Networking Interconnect, Inphi

As the massive megatrends of cloud computing, Big Data, IoT, Social and Web2.0 continue to accelerate and drive the insatiable need for bandwidth, there is clear need to increase speed while maintaining cloud economics and lowering carbon footprints. PAM4 modulation has been recognized as the modulation scheme for the next wave of Ethernet deployments for optical and copper interconnects by doubling the bits per symbol at the same baud rate. We will explore how new technologies and higher order modulation schemes, like PAM4, will drive the future deployment of 100G networks.

Gearbox and Retimer PHYs with RS-FEC for Flexibility and Performance
John Monson, Vice President of Marketing, MoSys

Interoperability and utilization are critical requirements for cost and power efficiency for connecting today's cloud networks. With the transition from 10/40G to 25G/100G, several standards have evolved to ensure compatibility, signal integrity, and increased capacity. New optical and electrical standards specify Clause 91 RS-FEC and multi-link capability to enable compatibility, density, transmission distance and data integrity. MoSys' LineSpeed Flex family is designed to cover the wide range of gearbox and retimer requirements using a common set of footprints and software.

There will be Q&A and a panel discussion featuring above speakers.



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