Linley Processor Conference 2017
Covers processors and IP cores used in deep learning, embedded, communications, automotive, IoT, and server designs.
Held October 4 - 5, 2017
Proceedings available

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Agenda for Day One: Wednesday October 4, 2017
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Processor Innovation Supersedes Moore’s Law
Linley Gwennap, Principal Analyst, The Linley Group

As Moore's Law slows, innovations in processor design become more important than ever before. As deep learning moves from the cloud into client devices such as automobiles and voice-operated devices, processors are evolving to more efficiently handle this new application. Data-center operators can choose from new server-processor suppliers even as they roll out NFV and new security technologies. FPGAs show promise for accelerating a variety of changing workloads. New instruction sets, IP cores, and development tools simplify SoC design. This keynote presentation will address these and other processor-design trends.

9:45am-10:30amSession 1: Neural Networks and Vision Processing

Neural networks are a critical component of most deep-learning systems and are used for tasks ranging from natural language processing to object recognition. The latter task is often combined with vision processing, particularly in automobiles and security cameras. This session, led by The Linley Group senior analyst Mike Demler, will examine the IP cores available to simplify the design of client SoCs and show how these functions work in a complete SoC product.

Versatile Deep-Learning Vision Platform for Mobile, Surveillance, and Automotive
Yair Siegel, Director of Marketing, CEVA

Computer vision, deep learning and AI have become indispensable technologies in everyday consumer products. Dual-camera smartphones, smart-home sensors, and ADAS have come to rely on low-power vision processing for computational photography, object recognition, and autonomous vehicles. CEVA's vision platform includes hardware IP and deep-learning software frameworks and libraries to help designers efficiently bring their algorithms into embedded products. This presentation will address the implementation of embedded neural networks and computational-photography algorithms using this platform, including examples from recent consumer products.

Tight Integration of Pixel Processing and Deep Learning for Embedded Vision
Gordon Cooper, Product Marketing Manager, Synopsys

As the number of pixels in cameras increases, embedded vision-processing performance requirements are rising, algorithms are getting more complex, and power and area goals remain aggressive. Engineers looking for the most optimized performance and power solution are turning toward high-performance embedded vision processors tightly coupled with dedicated neural-network engines. This presentation will describe how embedded vision processors, offering a combination of tight integration and scalability, can efficiently support high-performance vision applications such as surveillance, autonomous driving, and augmented reality.

10:30am-10:50amBREAK – Sponsored by AMD
10:50am-12:30pmSession 1: Neural Networks and Vision Processing (cont)

Scaling Up Vision and Imaging DSP Performance
Pulin Desai, Director Vision and AI Product Marketing, Cadence

This presentation will disclose details of a new multipurpose vision- and neural-network-optimized DSP core, including enhancements in processor pipeline, memory subsystem, and data-management systems. The discussion will include details on uniprocessor and multiprocessor scaling to meet the rapidly growing demands of imaging and vision systems in mobile, consumer, automotive and security markets.

Desired Characteristics of Tomorrow’s High-Performance Embedded Neural-Network Accelerators
Márton Fehér, Head of aiWare, AImotive

Neural-network evolution started with relatively easy computational tasks like speech recognition and classification of small images. Targeted hardware-accelerator development focused on these areas and workloads. However, today's advanced DNNs used for vision pose new challenges. While many industry players seek answers in their existing hardware, we believe current architectures and benchmarking techniques must be re-invented to build suitable accelerators for advanced DNNs. This new thinking is the key to making informed decisions about the relative performance of future architectures.

Evolving Camera and Machine Learning Processing
Rick Maule, Senior Director of Product Management

Benefiting from multiple years of vision DSP shipments in phones and other mobile devices, this presentation will highlight new innovations to improve both performance and power for vision processing for camera, machine learning, and other domains. In addition, the talk will highlight a programming model to make the use of vision processors significantly easier.

There will be Q&A and a panel discussion featuring above speakers.

12:30pm-1:50pmLUNCH – Sponsored by Synopsys
  Track A Track B
1:50pm-3:30pmSession 2: Processor IP

Although ARM remains the most popular CPU core, new technologies are emerging to challenge the market leader. This session, led by The Linley Group principal analyst Linley Gwennap, discusses recent innovations from ARM to improve the design of heterogeneous processors. It also features the announcement of a new high-end RISC-V CPU a unique low-power graphics core.

Ultralow-Power 3D Micro-GPU for IoT-Class Devices
Iakovos Stamoulis, Director Engineering Management, Think Silicon S.A., An Applied Materials Company

The emerging Internet-of-Things market--with display devices limited in area, performance, memory, thermal dissipation and battery capacity-- adds design challenges for engineers. For these new display devices, the end user expects the same fluid interaction and high-quality GUI experience of their smartphones/tablets. The NEMA Series of ultralow-power micro-GPU cores bridges this gap, offering high-quality graphics in resource-constrained devices while improving battery life by up to 50x compared to some existing GPUs.

Arm DynamIQ: Scalable SoCs for Networking, Automotive, and Embedded Applications
Brian Jeff, Senior Director of Product Management, Arm

The nature of compute is changing from the edge to the cloud. The ever-increasing performance demands, while improving efficiency, require a new approach to how CPUs are designed for cluster-based multiprocessing. This talk describes how DynamIQ technology can deliver tailored performance for key growth areas in embedded, automotive, and infrastructure. Learn how the latest DynamIQ-based Cortex-A CPUs enable new performance levels, new configuration options, power-saving methodology, and redesigned memory to improve SoC designs.

Introducing the New RISC-V U54 Coreplex
Jack Kang, VP of Product Marketing, SiFive

In this presentation, SiFive, a founding member of the RISC-V Foundation, will introduce the U54 Coreplex, a multi-core 64-bit application-processor-class RISC-V CPU. The new design supports a quad-core configuration featuring a coherent L2 cache, support for the latest RISC-V specifications (including RV64GC, machine, supervisor, and user privilege modes), and external debug support. The new CPU supports Linux, Unix, FreeBSD, and other advanced operating systems in the RISC-V ecosystem.

There will be Q&A and a panel discussion featuring above speakers.

Session 4: Networking and Comms

Software-defined networking (SDN) and network-function virtualization (NFV) are disrupting traditional network architectures. This session, led by The Linley Group principal analyst Bob Wheeler, will discuss related advances in network processing spanning server, switch, and edge applications.

Networking Intelligence at the Server Edge
Bob Doud, Sr. Director of Marketing, Mellanox

An ever-increasing torrent of network traffic, security threats and complex protocol manipulation is placing huge demands on the CPUs in today's servers. Networking intelligence must be pervasive and distributed throughout the data center to be effective and scalable. Advanced networking adapters can dramatically offload server workloads, while simultaneously enforcing security as a gatekeeper to the server. This presentation will describe intelligent networking solutions including accelerated adapters and the BlueField multicore ARM-powered software-defined NICs.

Enabling Enterprise-Class vCPE and Multi-Access Edge Computing
Toby Foster, Senior Product Marketing Manager, NXP

Building on its momentum in SOHO and central office settings, NFV is coming to high-end enterprise routers and the access network. Processors for enterprise-class virtual CPE (vCPE) and multi-access edge computing (MEC) require a different balance between performance and power consumption than either SOHO vCPE or classic NFV workloads. At the same time, these processors must all be compatible and based on an open architecture to enable the distributed intelligence that characterizes the new virtual network. This presentation will announce a new processor to address these needs.

Extending a Proven Path for High-Bandwidth Networking
Andreas Schlapka, Director of Networking, Micron

Graphics memory presents the most compelling cost-to-performance memory solution to address the aggressive bandwidth requirements of high-end networking applications. The upcoming JEDEC GDDR6 standard builds on the proven success of prior generations, providing a path toward a remarkable 1 TB/s of system memory bandwidth. This talk will discuss real-world networking applications leveraging the system-level benefits of GDDR and how this new memory standard sets a course for system designers to significantly increase bandwidth to address the demands of next-generation platforms.

There will be Q&A and a panel discussion featuring above speakers.

3:30pm-3:50pmBREAK – Sponsored by AMD
3:50pm-5:00pmSession 3: Automotive Safety

As we move rapidly into the era of self-driving cars, automakers need much greater levels of processing power than in current vehicles. But in tapping new processor suppliers, automakers must ensure that these new products meet strict safety standards. This session, led by The Linley Group senior analyst Mike Demler, will discuss how to build processors that meet automotive safety standards using licensed IP cores.

High-Performance Processors for Safety-Critical Applications Drive Smart Automotive Applications
Mike Thompson, Sr. Product Marketing Manager, ARC Processors, Synopsys

Automotive capabilities for advanced driver assist systems (ADAS) are advancing rapidly because of the potential that they offer to enhance safety and simplify the driving process. The high-performance processors that are used to build these systems are key in the certification effort for the systems. This presentation will look at the safety enhancements and ASIL certification support that are available for the high-end ARC processors.

Enabling Mixed-Protocol Heterogeneous Cache Coherency and ISO 26262 Functional Safety
Sanjay Deshpande, Director of Cache Coherency and Interconnect Architecture, Arteris IP

Autonomous driving requirements are mandating the simultaneous use of multiple types of processing units to efficiently execute sophisticated image processing, sensor fusion, and machine learning/AI algorithms. This presentation introduces new coherency platform technology that enables the integration of heterogeneous cache coherent hardware accelerators and CPUs, using a mixture of ARM ACE, CHI, and CHI Issue B protocols, into systems that meet both the requirements of high compute performance and ISO 26262-compliant functional safety.

There will be Q&A and a panel discussion featuring above speakers.

Session 5: Platform Security

With seemingly every day bringing new reports of ransomware, spyware, and other cyberattacks, improving device security is essential. This session, led by The Linley Group senior analyst Tom Halfhill, will discuss how processor vendors and IP vendors are developing new capabilities to protect against malicious software in both servers and client devices.

EPYC: Enabling a More Secure World
Piotr Weglicki, Sr. Product Marketing Manager, EMB Thin Client Marketing, AMD

Closing the door to existing and future security threats requires more than improved software. New forward-looking hardware capabilities must be part of the equation. EPYC processors introduce new memory-encryption capabilities never before seen on mainstream server processors. This presentation will review these new capabilities, the secure hardware foundation upon which it is built, and why it is essential to addressing threats to existing and emerging memory technologies.

Architecting Future-Proof Platform Security from Device to Cloud
Winthrop Wu, Technical Director, Cryptography Research Division, Rambus

In today's always-connected world, security is a critical component in any new product. Security historically meant protecting the WAN through communications security (IPsec/SSL) and user authentication, but this still allows attacks on the endpoint, where data is stored in the clear and applications are vulnerable. In this presentation, we will highlight some common security architectures, show where they have security gaps, and discuss potential methods for plugging those gaps, including hardware root-of-trust, key provisioning, security-as-a-service, and device monitoring.

There will be Q&A and a panel discussion featuring above speakers.

5:00pm-6:30pmReception and Exhibits – Sponsored by Synopsys


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