Linley Fall Processor Conference 2019

Held October 23 - 24, 2019
Proceedings available

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Agenda for Day Two: October 24, 2019
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9:00am-9:50amKeynote Session:

Challenges and Opportunities of Architecting AI Systems at Data-Center Scale
Misha Smelyanskiy, Director of AI System Codesign Group, Facebook

The rapid growth of AI has stressed all major components of the traditional datacenter infrastructure, such as compute, memory, storage and fabric. Containing this unsustainable infrastructure growth requires codesign of innovative AI software and hardware platforms. This talk will describe the challenges of building high-performance energy-efficient platforms in the presence of evolving AI workloads. It will also discuss how to address these challenges, providing some concrete examples of Facebook's solutions.

There will be a brief Q&A with the speaker.

9:50am-10:30amSession 7: SoCs for Edge Devices

As network-edge devices and local clients offload more processing from the network core, chip vendors are striving to meet demands for higher performance within a manageable power envelope. Machine learning and 5G pile even heavier workloads on these systems. This session, moderated by The Linley Group senior analyst Tom R. Halfhill, presents several new products and technologies for higher-performance embedded systems and mobile clients.

A Processor for 5G Open RAN Systems
Toby Foster, Senior Product Marketing Manager, NXP

5G cellular networks differ from their predecessors not only technically, but also in the vendor landscape. Just as white-box switching disrupted networking gear, the Open Radio Access Network (ORAN) Alliance will disrupt wireless networks. Based on virtualized network elements, white-box hardware, and standardized interfaces, ORAN systems enable interoperable multivendor autonomous RAN equipment. This presentation describes how the 16-core LX2106A processor can perform central unit (CU) and distributed unit (DU) Layer 2 and Layer 1 functions in an ORAN system.

Introducing Intel Tremont Microarchitecture
Stephen Robinson, Senior Principal Engineer – Tremont Architecture, Intel

The Tremont CPU architecture was designed for enhanced processing power in compact, low power packages. Products based on Tremont will span both client, IOT and Data Center products and combined with broader Intel portfolio of IPs Tremont will power a new generation of Intel products across the compute offering. This presentation will unveil, for the first time publicly, the details of the micro-architecture of Tremont as well as briefly touch on the implementation of Tremont with other Intel compute cores.

10:30am-10:50amBreak - Sponsored by SiFive
10:50am-12:45pmSession 7: SoCs for Edge Devices (cont.)

Scalable IP for High-Performance Configurable SoC Design
Krste Asanović, Co-Founder & Chief Architect, SiFive

The convergence of AI, 5G, and data analytics is driving the need for diverse computing solutions in many markets. In this talk, SiFive will detail new, high-performance processor core IP with significant compute capability enhancements to meet the needs of the high-performance workloads. Modern compute workloads are rapidly evolving to require the ability to scale performance on-demand and have real-time, deterministic requirements which demand scalable solutions beyond what legacy architectures provide.

The Next Level of Performance and Energy-Efficient Edge Computing
Simon Craske, Lead Embedded Architect and Fellow, Arm

End-point devices face ever-increasing demands for digital signal processing (DSP) and machine-learning (ML) capabilities. The M-Profile Vector Extension (MVE) addresses these demands by improving the CPU's DSP and ML performance, eliminating the need for separate DSP processors, disparate toolchains, and heterogeneous development environments. MVE delivers single-instruction multiple-data (SIMD) capabilities while retaining low interrupt latency, low gate count, and energy efficiency.

Designing a GPU for the 5G Era
Kristof Beets, Senior Director of Product Management & Technology Marketing, PowerVR Graphics, Imagination

The introduction of 5G is increasing the complexity of mobile SoCs. The resulting rise in power requires doubling down on efficiency at the IP level. This presentation will show how next-generation PowerVR GPUs answer this challenge using more sophisticated compression (including HDR and memory handling), power optimization and management, multi-tasking, and scalability.

There will be Q&A and a panel discussion featuring above speakers.

12:45pm-2:00pmLunch - Sponsored by Intel
2:00pm-3:30pmSession 8: AI at the Edge

Neural-network accelerators offer numerous options for designing AI-powered edge devices, but selecting the one best suited to a particular application is challenging. Many vendors use purpose-built digital designs, while others are developing neuromorphic architectures modeled after the human brain. This session, moderated by The Linley Group principal analyst Linley Gwennap, will discuss new hardware-software solutions for improving AI performance and power efficiency in edge devices.

Edge Inference Architecture for High Throughput at Low Power and Low Cost
Cheng Wang, Sr. VP, Software, Architecture, Engineering, Flex Logix

Edge inference needs to run on large models with megapixel images to achieve accurate predictions, but it must also run with batch=1 for low latency. The target throughput must be achieved within power and cost budgets. This presentation will describe the InferX X1 architecture, which can deliver high throughput per watt and throughput per dollar for typical edge applications.

A Graph-Based Dataflow Architecture for Executing Neural Networks
Dave Fick, CTO and founder, Mythic

Neural networks are graph-based applications with opportunities to execute many graph nodes concurrently. Recent architectures have responded with massively parallel systems, but scheduling them has proved challenging, often relying on an oracle compiler. Instead, Mythic created an architecture that works on graphs directly: producer/consumer relationships are hardware concepts, and parallel execution happens automagically when dependencies are met. This presentation discloses a high-level overview of the architecture and how it can efficiently achieve parallelism on a wide variety of neural networks.

Introducing Akida: An Event-Based Processor
Anil Mankar, Chief Development Officer, Brainchip

This presentation will introduce Akida, an event-based reconfigurable multicore neural-network processor. It processes data in the form of spikes, which have a temporal and spatial distribution. Power is consumed only when spikes are processed. The device can run inference for standard convolutional neural networks trained with back-propagation in an event-driven environment. The same device can also use on-chip learning methods to run training and classification for native spiking neural networks, reducing power and memory requirements in edge IoT devices.

GrAI One – NeuronFlow Processing for the Edge
Jonathan Tapson, Chief Scientific Officer, GrAI Matter Labs

NeuronFlow draws from both neuromorphic and dataflow paradigms to address real-world AI applications such as autonomous navigation and cognitive assistants. It implements sparse processing of real-time data to improve latency and power efficiency. GrAI One is GML's first NeuronFlow-based chip, expected in 2020. The presentation will introduce the chip's architecture and provide performance and power benchmarks.

3:30pm-3:50pmBreak - Sponsored by SiFive
3:50pm-5:00pmSession 8: AI at the Edge (cont.)

Bringing Native AI Processing to the Edge
Chien-Ping Lu, CTO, NovuMind

With repurposed Von Neumann processors reaching their limits in the AI industry, we are entering the third phase of hardware evolution with the introduction of domain-specific architectures for efficient AI processing. This presentation will detail the company's NovuTensor architecture that has been designed to improve neural-network performance, efficiency, and scale for edge applications. This architecture can perform native tensor processing and calculations with hierarchical tensor data with low overhead, high efficiency, and with multi-dimensional scalability.

There will be Q&A and a panel discussion featuring above speakers.

5:00pmEnd of Conference

 

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