The combination of scalable vector processing with a Linux-capable superscalar multi-core processor opens up a wide range of design points and applications for RISC-V. This presentation describes a new processor core that features a complete implementation of the latest RISC-V Vector (RVV) extension. SiFive Intelligence is slated for production use based on the fully ratified version of the RVV specification and enables a single development environment for scalar and high-performance vector processing applications.

The NX27V vector processor has 9 functional units and integrates the scalar FPU. Fourteen vector instructions can be concurrently executed. Innovative design algorithms are used to issue 8 micro-ops per cycle and allow vector instructions to be chained, executed, and completed out-of-order without the use of any temporary registers. This CPU IP can sustain performance of 96 GFLOPS, yet it was designed from start to final delivery in just 9 months by a small design and verification team.

Modern 5G RAN baseband processing introduces formidable computing challenges. Physical-layer processing requires handling multiple data and control channels, and it must enforce extremely short latency. 5G baseband computing platforms must cope with both massive spectrum allocations for a single user and granular narrow allocations for many users. This situation creates a huge challenge for efficient resource utilization in a highly parallel DSP. This presentation explores the CEVA-XC16 vector DSP, which introduces a novel and unique multicore dynamic multithreading scheme.

Machine-learning solutions seek to train and deploy ML models in a timely and cost-effective manner. This presentation describes Groq’s scale-out system architecture for large-scale machine learning. We provide a brief overview of the chip microarchitecture and protocols for interchip communication. We discuss data decomposition and model partitioning in the context of the chip’s partitioned global address space (PGAS) and provide some early performance results scaling across multiple chips using NLP models like BERT.

The machine learning field is red hot, and numerous teams have been striving to discover and implement the ideal computer architecture for neural network computations. The breadth of exploration has been impressive, and several new ideas have produced working silicon. While everybody knows that hardware is hard, the software component of the complete solution has emerged as an even greater challenge. Producing performant graph compilers has, in particular, proven elusive. This presentation describes our holistic approach to hardware/software architecture.

AI will be everywhere from serving burgers to launching space stations. AI hardware acceleration is also everywhere from CPUs and GPUs to special-purpose AI processors to support compute demand from device, client, and edge to the cloud. This presentation discusses the role of software in delivering the peak performance of Intel AI hardware, enabling end-to-end pipelines on diverse heterogeneous hardware through OneAPI, and in breaking barriers for data scientists and developers to apply AI through automated and unified software tools.