Linley Fall Processor Conference 2020

Held October 20-22 and 27-29, 2020
Proceedings available

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Agenda for Day Two: Wednesday October 21, 2020
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8:30am-10:00amSession 2: Vector-Processing Cores

Many applications—including signal processing, image processing, and neural networks—benefit from parallel processing of vector data, often referred to as SIMD (single instruction, multiple data) processing. Digital signal processors (DSPs) traditionally handle vector processing, but many CPUs now include vector units, enabling them to combine high-level operating systems and high-performance SIMD in a single core. This session, moderated by The Linley Group principal analyst Linley Gwennap, discusses two CPU cores that implement the new RISC-V vector extensions as well as a licensable vector-DSP core.

Extending AI SoC Design Possibilities Through Linux-Capable Vector Processors
Krste Asanović, Cofounder & Chief Architect, SiFive

The combination of scalable vector processing with a Linux-capable superscalar multi-core processor opens up a wide range of design points and applications for RISC-V. This presentation describes a new processor core that features a complete implementation of the latest RISC-V Vector (RVV) extension. SiFive Intelligence is slated for production use based on the fully ratified version of the RVV specification and enables a single development environment for scalar and high-performance vector processing applications.

A RISC-V OOO Vector Processor
Thang Tran, Principal Engineer, Andes Technology

The NX27V vector processor has 9 functional units and integrates the scalar FPU. Fourteen vector instructions can be concurrently executed. Innovative design algorithms are used to issue 8 micro-ops per cycle and allow vector instructions to be chained, executed, and completed out-of-order without the use of any temporary registers. This CPU IP can sustain performance of 96 GFLOPS, yet it was designed from start to final delivery in just 9 months by a small design and verification team.

Addressing 5G Intelligent RAN Using a Dynamically Multithreaded Vector DSP
Nir Shapira, Business Development Director, CEVA

Modern 5G RAN baseband processing introduces formidable computing challenges. Physical-layer processing requires handling multiple data and control channels, and it must enforce extremely short latency. 5G baseband computing platforms must cope with both massive spectrum allocations for a single user and granular narrow allocations for many users. This situation creates a huge challenge for efficient resource utilization in a highly parallel DSP. This presentation explores the CEVA-XC16 vector DSP, which introduces a novel and unique multicore dynamic multithreading scheme.

For this session, each talk will have 10 minutes of Q&A immediately following.

10:00am-10:10amBreak Sponsored by SiFive
10:10am-11:40amSession 3: Advancing Cloud AI

As AI accelerators start to reach power limits, software and scale-out systems become critical to ongoing performance gains. This session, led by The Linley Group principal analyst Bob Wheeler, will discuss how vendors are addressing these challenges to AI’s progress in data centers and beyond.

Delivering Machine Learning at Scale
Dennis Abts, Chief Architect, Groq

Machine-learning solutions seek to train and deploy ML models in a timely and cost-effective manner. This presentation describes Groq’s scale-out system architecture for large-scale machine learning. We provide a brief overview of the chip microarchitecture and protocols for interchip communication. We discuss data decomposition and model partitioning in the context of the chip’s partitioned global address space (PGAS) and provide some early performance results scaling across multiple chips using NLP models like BERT.

Relegating the Important Stuff to the Compiler
Ljubisa Bajic, CEO and Lead Architect, Tenstorrent

The machine learning field is red hot, and numerous teams have been striving to discover and implement the ideal computer architecture for neural network computations. The breadth of exploration has been impressive, and several new ideas have produced working silicon. While everybody knows that hardware is hard, the software component of the complete solution has emerged as an even greater challenge. Producing performant graph compilers has, in particular, proven elusive. This presentation describes our holistic approach to hardware/software architecture.

Software for AI Everywhere
Wei Li, VP, Chief Architect for Machine Learning Software, and General Manager of Machine Learning Performance, Intel

AI will be everywhere from serving burgers to launching space stations. AI hardware acceleration is also everywhere from CPUs and GPUs to special-purpose AI processors to support compute demand from device, client, and edge to the cloud. This presentation discusses the role of software in delivering the peak performance of Intel AI hardware, enabling end-to-end pipelines on diverse heterogeneous hardware through OneAPI, and in breaking barriers for data scientists and developers to apply AI through automated and unified software tools.

There will be Q&A and a panel discussion featuring the above speakers.

11:40am-12:40pmBreakout sessions with today's speakers
1:30pm-3:30pmSpeaker 1:1 Meetings


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