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HPE Reveals Gen-Z Fabric Chipset

September 17, 2019

Author: Bob Wheeler

Occasionally, standards take on a life of their own. With Gen-Z, what started as a simple concept has exploded into a full-blown fabric standard. That original concept was to split processor memory controllers by moving media-specific functions to the memory module. Not only would it decouple memory technology from the processor, but the high-speed serdes interface would reduce pin count or enable greater memory bandwidth. In addition to point-to-point (P2P) links, however, Gen-Z works with many different topologies, including switch fabrics. In fact, it has grown into a multipurpose fabric that can handle byte-addressable memory, block storage, and even interprocess communications.

At Hot Chips, Hewlett Packard Enterprise (HPE) Fellow Patrick Knebel presented the industry’s first Gen-Z chipset, which targets exascale fabrics. Because no processor yet integrates a Gen-Z interface, the company developed a bridge chip that connects a PCIe Gen4 host to its optical fabric. It also developed a 12.7Tbps switch chip that sports in-package optics. Gen-Z lacks an optical-link specification, so the fabric’s physical layer is proprietary. The internal-ASIC designs are intended for prototype quantities—HPE hasn’t disclosed plans for commercial-system availability.

Owing to its target application, the chipset competes with high-performance-computing (HPC) interconnects rather than memory or storage interfaces. Its Gen-Z memory semantics, however, set it apart from fabrics that support only message passing. In that respect, it’s another step in HPE’s memory-driven-computing thrust, which grew out of a Hewlett Packard Labs project called “The Machine.” Although it’s also the first Gen-Z chipset, we expect mainstream designs for the protocol will be far less ambitious.

Subscribers can view the full article in the Microprocessor Report.

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