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Micron Reinvents DRAM Memory

September 12, 2011

Author: Jag Bolaria

Micron’s Hybrid Memory Cube (HMC) is a radical departure from the traditional DRAM architecture. It uses a combination of 3D packaging technology, repartitioned system functions, and high-speed serdes connectivity on the chip. The 3D technology uses TSVs (through-silicon vias) and microbumps to stack multiple die in a single package. By stacking multiple die, the HMC quadruples the memory capacity compared with a monolithic die. Relative to external connectivity of DRAM chips or wire-bond connectivity in a single package, TSV technology reduces connectivity impedance and thus the total power per bit.

Not satisfied with the benefits of using TSV stacked die, Micron decided to re-architect system memory. The HMC creates many more banks than traditional DRAM does, meaning it can support more requests and multiple hosts. The HMC moves the memory controller from the processor to the memory device. This repartitioning allows the HMC memory controller to more efficiently interact with the memory array. It also allows the memory to play a central role in the system by supporting multiple hosts or by creating a mesh of interconnected HMC devices.

Micron is not alone in developing 3D stacked die for future memories. Samsung and Elpida have also disclosed plans to offer 3D memory in about the same timeframe that Micron is using. Samsung is pursuing space-constrained markets such as smartphones, whereas Micron is pursuing networking and high-performance computing. Samsung is primarily relying on 3D technology to reduce the size of the memory chip; Micron plans to redesign the memory architecture, including the packaging, memory partitioning, and memory interface.
DRAM technology has not kept pace with the requirements of networking and high-performance computing (HPC). Micron’s HMC reworks the entire DRAM subsystem to better address future memory requirements. Although the HMC is an exciting product with huge potential, it faces significant technical and business hurdles. TSVs are a new technology that add manufacturing risk and cost. To establish a new standard memory interface, Micron must enlist support from third-party processor vendors. Solving this business issue may be more difficult than resolving the technology risks.

Microprocessor Report Subscribers can view the full article here: http://www.mpronline.com/mpr/h/article.php?id=10803

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