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Achronix Speedster 22i Has More I/O

May 11, 2012

Author: 4

Established on the premise that asynchronous circuits make the best FPGAs, Achronix surprised the industry when it recently revealed details of its new Speedster 22i family. While one branch of the family propagates the asynchronous technology, another steps in time with the rest of the industry by using conventional synchronous logic.

The synchronous high-density (HD) members integrate 100,000 to 1,100,000 four-input look-up tables (LUT4s) and target peak performance of 750MHz (500MHz typical). The largest FPGA from Altera closest to the HD line in I/O capability has only 622,000 logic elements. The best comparable Xilinx chip has 876,160 logic cells. (Logic cells and elements are roughly LUT4-equivalents.)

Achronix plans to sample the first HD chips in September 2012. Due to sample in 1Q12, the asynchronous high-performance (HP) members integrate 140,000 to 250,000 LUT4s and operate at the equivalent of 1.5GHz peak (1.2GHz typical). Both HD and HP lines have extensive high-speed I/O, with the package of the top-end HD1500 having 2,597 balls—more than twice as many as rivals’ leading FPGAs.

These balls enable the HD1500 to simultaneously support 960 general-purpose I/Os, (GPIOs), 16x28Gbps serdes, and 64x13Gbps serdes. In comparison, Altera has no device with more than 4x28Gbps serdes, and it has only 600 GPIOs. Xilinx has a chip with 16x28Gbps serdes, but it too has only 600 GPIOs. 600 GPIOs sound like a lot, but a memory-intensive design can consume these pins. In addition to these physical-layer capabilities, the Speedster 22i devices integrate I/O controllers for 100G Ethernet, Interlaken, PCIe Gen3, and DDR3 SDRAM. The competing chips with 28Gbps serdes do not integrate Ethernet or Interlaken controllers.

Influencing Achronix’s decision to develop a conventional FPGA was its use of Intel’s foundry services. Without a differentiated product, no one would choose a startup’s FPGA over established suppliers’ offerings. Before the Speedster 22i, Achronix distinguished its parts by their performance, achieved through asynchronous logic. Gaining an advantage in process technology by working with Intel, Achronix now has the opportunity to also differentiate on power and logic density—which affects cost and the number of programmable gates available.

Most FPGA startups have met quiet demises. It’s a tough business and many things can go wrong. Promising new chips become dated when the startup suffers a schedule slip. A narrow product line fails to match up with established suppliers’ broad portfolios. Software fails to conform to customers’ design flow. Achronix seeks to buck the trend. Use of Intel’s fabs gives the company an important advantage. Speedster 22i will still be way ahead in process technology although it is coming to market later than Altera’s Stratix V and Xilinx’s Virtex 7. The startup still faces technical risk. Delivering the HD and HP line—both being large, complex designs integrating leading-edge I/O—is a difficult engineering feat.

Spanning a wide range of densities, offering more gates than rivals’ serdes-enabled FPGAs, uniquely integrating copious I/O controllers, and offering a high-performance option based on its signature asynchronous logic, Achronix offers differentiated products backed by Intel’s manufacturing might. Achronix is thus the most promising high-performance FPGA startup to emerge in years. But watch out: startup Tabula is working with Intel, too.


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