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ARM's 64-Bit Makeover

December 24, 2012

Author: Tom R. Halfhill

ARMv8 is the most extensive modification ever wrought on an established CPU architecture since Intel's Itanium. In effect, it's an entirely new 32- and 64-bit ISA. In the extent of its changes, ARMv8 is radical. In another way, however, ARMv8 is more conservative. It hews close to traditional RISC canons, ditching heretical concepts such as preshift and conditional execution.

Although ARM cores have always been power-efficient designs, the original architecture deviated from the purists' RISC philosophy and has accumulated more complexity over the years. Consequently, today's CPUs retain some features that made sense two decades ago but later became handicaps. ARMv8, therefore, is subtractive as well as additive.

What's missing? All Aarch64 instructions are 32 bits long, omitting 16-bit Thumb instructions. Consequently, code density may be worse, but instruction decoding is simpler (and therefore faster), and memory alignment is tighter. ARM's logical assumption is that applications requiring 64-bit processing need higher performance more than they need smaller binaries, because memory keeps getting cheaper and faster. If code density is important, the processor can switch to Aarch32 mode and use the T32 subset of 16/32-bit Thumb instructions.

Until now, a defining characteristic of the ARM architecture was conditional or predicated execution. Most instructions (not just conditional branches) could discard their results depending on the condition of a status flag. These conditional instructions eliminate some explicit branches and therefore the potential for misprediction. On the downside, the additional logic circuitry of conditional execution complicates implementation and impedes high-speed pipelining. Aarch64 largely eliminates conditional execution in favor of a larger addressable register file.

The 32-bit mode, called Aarch32, deprecates several existing instructions and features. "Deprecate" means these instructions are implemented in the hardware, but software is advised not to use them, because future versions of the architecture may not support the deprecated features. Some examples include the fast context-switch extension, VFP short vectors, and the Jazelle DBX (Direct Bytecode eXecution) extensions for Java. Jazelle RCT, a lesser extension, is optional.

At some point, future CPUs will probably stop supporting ARMv8's deprecated features. Such a design would break compatibility with older 32-bit binaries but also eliminate the additional logic required to support them. By deprecating instead of eliminating features, ARMv8 retains all of ARMv7's instruction complexity, so it's unclear how much hardware efficiency will be gained. Deprecation simply sets the stage for simpler hardware designs in the future.

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