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Linley Newsletter

Getting Way Out of the Box

August 5, 2013

Author: Linley Gwennap

Some people say there’s nothing new under the sun, but they haven’t talked to a group of rogue CPU architects that have dubbed themselves Out-of-the-Box Computing (OOTBC). Their design is so far out, they can barely see the box. After a decade of work, the team members have begun to talk publicly about the Mill. The project targets general-purpose application code, such as for servers, PCs, and tablet computers.

An important feature of the design is its lack of traditional registers. Hot data is stored on the “belt,” which is similar to a stack but offers important advantages. Without registers, the CPU needs no register renaming, greatly reducing the amount of overhead logic and busing. To boost performance, the Mill uses a VLIW-style design to encode up to 33 operations per instruction. Decoding so many operations in a single cycle is a challenge that the team has met using two program counters, one of which runs backward.

The Mill is a scalable architecture that can address multiple markets. The team has specified several family members, including a low-end design code-named Tin and a high-performance version called Gold. The company expects a dual-core Gold chip, in current 28nm technology, to deliver peak performance of 79 billion operations per second at 1.2GHz while dissipating about 28W (typical) for a basic processor design. As with most CPUs, this performance can be further scaled by adding more cores.

Assuming the Mill achieves its lofty performance goals, its performance per watt should be much better than traditional architectures. If we compare it with a 2.5GHz quad-core Haswell, the Mill’s advantage in peak performance is a respectable 3x. Unfortunately, OOTBC does not have a fully functional compiler and thus cannot provide any benchmark results.

Subscribers can view the full article in the Microprocessor Report.

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