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ARM Doubles Up on CoreLink

November 5, 2013

Author: Mike Demler

In 2012, ARM reinforced its assault on the enterprise computing market by introducing new CoreLink cache-coherent-network (CCN) IP. At the recent Linley Tech Processor Conference, the company announced the second-generation CCN-508, which increases the capacity of the CoreLink network compared with its predecessor to support up to 32 CPUs.

The first version, the CCN-504, enables users to create a high-performance multiprocessor by connecting up to 16 Cortex-A50-series CPUs in four cache-coherent clusters. The last digit in the CCN serial number designates how many clusters of ARM CPUs the fabric supports. Each cluster can contain up to four 64-bit Cortex-A57s or Cortex-A53s. CoreLink networks also support clusters of 32-bit ARM MPCores: Cortex-A7, A12, and A15.

The CCN-508 fabric increases support to eight clusters in heterogeneous combinations of CPUs, GPUs, DSPs, and hardware accelerators. ARM increased the maximum number of Amba 4 I/O ports from 18 to 24, maintaining support for AXI4 and Ace-Lite. It also increased the bus width to 256 bits in the CCN-508—twice that of the CCN-504.

ARM is just beginning to engage with customers for the CCN-508, and it expects the first SoCs using this IP to enter production in late 2014 or early 2015. By providing performance and capacity improvements in its CoreLink CCN fabric and DMC memory controllers, the company is ensuring that Cortex-A50-based SoCs have the necessary bandwidth to scale from small-cell base stations to higher-performance network-infrastructure applications.

Subscribers can view the full article in the Microprocessor Report.

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