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Startup Taps OpenRisc for Booster

December 17, 2013

Author: Loring Wirbel

Cellular-repeater startup Nextivity used an Altera/Synopsys Nios CPU core, synthesized in an ASIC, for two generations of what it calls the Intelliboost Baseband Processor. This product serves in Cel-Fi, the company’s indoor-coverage extender for heterogeneous networks (hetnets). But for its third-generation Cel-Fi system, Nextivity designed its own proprietary processor using six CPU cores based on the OpenRisc OR1200.

Cel-Fi boosters are cellular-repeater systems for homes and small businesses. Users place a window unit housing the network CPU indoors where the cellular signal is strongest. This unit filters, boosts, and retransmits the signal using the unlicensed 5GHz band to a companion distribution unit positioned where the signal is weakest. The retransmitted signal supports up to four 20MHz cellular RF bands carrying any combination of WCDMA, HSPA+, and LTE.

Nextivity engineers considered a single-chip processor incorporating six ARM9 cores based on the ARMv5TE ISA, but they instead turned to OpenRisc for greater flexibility and lower licensing costs. OpenRisc is the flagship design of the OpenCores community, a Linux coalition formed in 1999. OpenRisc 1000 is an architectural description of a family of 32- and 64-bit processors, and OpenRisc 1200 (OR1200) is its first instantiation, written in Verilog. So far, Beyond Semiconductor, Orsoc, and Samsung have developed commercial OR1200 implementations, although Cadence also uses the synthesizable core as a reference design for EDA tools.

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