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EZchip’s Tile-MX Grows 100 ARMs

March 3, 2015

Author: Tom R. Halfhill

Boasting 100 CPUs, EZchip’s new Tile-Mx100 is by far the largest 64-bit ARM processor yet announced. It weaves the Cortex-A53 cores together in a cache-coherent mesh network that also includes packet accelerators, cryptography engines, memory controllers, and high-speed I/O interfaces. Intended for 100Gbps data-plane networking and network-function virtualization, the Tile-Mx100 significantly raises the bar for manycore ARM designs.

It’s also the first fruit reaped from EZchip’s $130 million acquisition of Tilera last year. The Tile-Mx100 follows the Tile-Gx family, whose largest member is the 72-core Tile-Gx8072. Although Tilera started the new design about a year before the acquisition, EZchip’s entry altered the project’s course in two important ways. First, the new owners decided to proceed with a Tilera skunk-works project to replace the company’s proprietary 64-bit VLIW cores with 64-bit ARM cores. Second, the Tile-Mx designers gained access to some accelerators that EZchip uses in its NP-5 and NPS-family NPUs.

EZchip unveiled the Tile-Mx100 at the recent Linley Data Center Conference. Like existing Tile processors, it is fully programmable in C/C++ and runs Linux with cache-coherent symmetric multiprocessing (SMP). The crucial difference is that the ARMv8 architecture opens up a wider selection of software and development tools than is now available for the proprietary Tilera CPUs.

The company plans to sample the Tile-Mx100 in 2H16 and begin production in 2017. Additional chips in the Tile-Mx family will have 36 or 64 cores. The new product line fulfills EZchip’s goal of using Tile processors to compete with Broadcom and Cavium while offering NPS-family NPUs for data-plane applications that demand even higher performance.

Subscribers can view the full article in the Microprocessor Report.

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