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Freescale Overhauls the Data Plane

July 21, 2015

Author: Tom R. Halfhill

Freescale is extensively overhauling its Data Path Acceleration Architecture (DPAA), a blanket term for the specialized packet-processing logic in QorIQ chips. Although the company announced DPAA2 last year, the full scope became clear during training sessions at the recent Freescale Technology Forum in Austin. DPAA2 is a major revision of the data plane that is more powerful, more flexible, and more programmable than the company’s previous designs.

DPAA2 was inspired by Nokia’s Open Event Machine, a model for nonblocking data-plane processing that supersedes conventional thread-based models in multicore processors. The industrywide OpenDataPlane initiative is loosely based on Open Event Machine and is promoted by Linaro, a consortium that develops open-source Linux software for the ARM architecture. OpenDataPlane also supports the Power, MIPS, and x86 architectures, and Freescale is implementing DPAA2 in all of its QorIQ processors, not just the ARM chips.

DPAA2 will debut in the QorIQ LS2085A and LS2045A, a pair of ARM-based communications processors that began sampling in 1Q15. It will also appear in the LS1088A and LS1048A as well as future Power Architecture and ARM chips.

Freescale hopes to achieve several goals with DPAA2. By offloading more tasks from the CPUs, the data-plane hardware improves performance and consumes less power and silicon than the ARM or Power CPUs would require for a pure software implementation. In addition, the abstract programming model enables Freescale to implement DPAA2 in different ways, such as omitting the regular-expression engine in the lower-end L1088A and LS1048A chips. DPAA2 thus enables QorIQ designs that are smaller, cheaper, and more power efficient than before.

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