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AMD Finds Zen in Microarchitecture

August 30, 2016

Author: David Kanter

The Zen microarchitecture offers a fresh start for AMD’s computing ambitions. It’s the company’s first CPU in a FinFET node, and it offers 40% higher IPC and power efficiency than the prior generation. Zen will serve in notebooks, desktops, and servers and will enable far more-competitive x86 products in 2017.

Zen is a dramatically better microarchitecture than the previous generation. In an era when a 10% improvement is huge, AMD had to rethink most of the CPU core. It added two-way simultaneous multithreading and abandoned the conjoined-core approach of the Bulldozer family. Each core integrates a new micro-op cache to avoid x86 decoding overhead, as well as a redesigned L1 cache with higher-performance and lower-power writeback caching, a private FPU and L2 cache, and many smaller modifications.

The basic integer pipeline is 19 stages using the conventional instruction fetch, which is similar to that of most high-performance cores. Zen is AMD’s first CPU to employ 14nm FinFETs, which should reduce the voltage to provide roughly 30% more power efficiency compared with older 28nm HKMG technology.

Today’s mainstream AMD products are based on the Bulldozer family, which also includes the Piledriver, Steamroller, and, most recently, Excavator CPUs. As a major upgrade, Zen will trigger a refresh across all the company’s product lines. In 1Q17, it’s scheduled to find a home in a new eight-core desktop-PC processor, code-named Summit Ridge, that is compatible with the existing AM4 socket. Slated to follow this design in 2Q17 is a 32-core server processor, code-named Naples. Last will come new notebook-PC processors in 2H17. AMD will announce product-specific details as these devices emerge, starting later this year.

Subscribers can view the full article in the Microprocessor Report.

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