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Adapteva’s Million-Dollar Epiphany

October 25, 2016

Author: David Kanter

Adapteva’s Epiphany-V is a 1,024-core test processor that should deliver 2Tflop/s of double-precision performance at 30W. More remarkably, it’s a 16nm FinFET design that took 10 months and less than $1 million to tape out on a multiproject wafer. The company hopes it will spur customer interest in licensing the CPU design.

The Epiphany-V CPU is an extremely simple two-issue microarchitecture with a five-stage pipeline and no virtual memory. It builds on the previous generation, adding a comprehensive 64-bit extension and new specialized instructions for machine learning, cryptography, and communications. The instruction set has been extended with 64-bit addressing in a flat, distributed, shared memory. Integer and floating-point (FP) instructions have been expanded to operate on 64-bit data. The cores are arranged in a symmetric 32x32 array connected through a three-channel mesh network-on-a-chip that uses 30-bit processor IDs.

Epiphany-V is a MIMD architecture that can be programmed using task-, data-, or pipeline-parallel models. Although Epiphany-V is not compatible with an OS that requires virtual memory (e.g., Linux), it can run real-time OSes and is supported by a version of GCC 5.9. The processor taped out recently, and first silicon is expected in 1Q17. We believe it will reach 1.0GHz for the core logic and 150MHz for the I/O pins, which translates to about 67Gflop/s of double-precision performance per watt—3.5x better than Nvidia’s P100.

Subscribers can view the full article in the Microprocessor Report.

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