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Microsemi Adds Midrange FPGAs

February 21, 2017

Author: Loring Wirbel

Microsemi is parlaying a long-standing advantage of its Igloo and SmartFusion FPGAs by making power dissipation and security two differentiating features in the new PolarFire family. This most recent line of midrange FPGAs ranges from 100,000 to 500,000 logic elements (LEs), each with a four-input lookup table and a D flip-flop, pitting it directly against popular alternatives such as the Xilinx Kintex 7.

The company relies on the nonvolatile silicon-oxide-nitride-oxide-silicon (Sonos) process, employing a UMC implementation based on a Cypress Semiconductor technology to deliver lower power dissipation than competing SRAM-based FPGAs. Its flash-memory-based design is also immune to soft errors (or single-event upsets) caused by alpha particles. The company proudly calls its competitive strategy “midrange” and has populated its 28nm PolarFire family with 12.7Gbps serdes rather than 28Gbps serdes.

By combining the low-power process with hard intellectual-property (IP) cores for high-level security as well as with faster serdes, Microsemi has positioned PolarFire above cost-optimized offerings such as the Intel Cyclone and Xilinx Artix families. In addition, it reduced the cost per LUT and the power dissipation relative to the 28nm Kintex and Arria families. The Intel and Xilinx 20nm lineups address higher densities but incur greater die costs and static power dissipation.

Microsemi says a Sonos-based 28nm CMOS process from UMC not only meets the goal of lowest static dissipation, but it also has an advantage over floating-gate flash memory and SRAM in active serdes-transceiver operation. Rather than design a serdes for 28Gbps, the company optimized it for 12.7Gbps, producing a smaller interface with lower power dissipation. This feature makes PolarFire the only FPGA architecture in which the logic fabric consumes most of the total device power—nearly 75%.

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