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Arteris Piano Tunes Timing

March 14, 2017

Author: Mike Demler

The Physical Interconnect-Aware Network Optimizer (Piano) 2.0 from Arteris offers new features to automate interconnect-timing closure in SoCs that employ the company’s network-on-a-chip (NoC) intellectual property (IP). The Piano tools help designers more quickly resolve clock skews and signal delays caused by the resistance, capacitance, and inductance of long on-chip wiring. Those unavoidable parasitic effects can degrade performance and cause malfunctions. Arteris licenses Piano as an optional package for users of its FlexNoC and Ncore products.

The company first addressed the timing-closure problem by releasing FlexNoC Physical, now called Piano. Timing closure typically requires multiple iterations, but Piano shortens that process by calculating a prelayout estimate of wire lengths and their delays, comparing the results with designer-specified constraints. It thus allows users to quickly determine whether the target specifications are even achievable and to identify where pipeline stages are required. The tool’s automatic pipeline creation helps users avoid inserting unnecessary register stages. The benefits are smaller die and lower power.

The first Piano only worked with the noncoherent FlexNoC, but Piano 2.0 adds the capability for designers to combine that interconnect with the coherent Ncore NoCs. Arteris also offers interconnect IP that’s compatible with ARM’s CoreLink products, but ARM’s cache-coherent networks lack NoC features and automation tools. The increased productivity that Piano affords will therefore attract many SoC designers to Arteris NoCs instead.

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