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AMD Teases Server Renaissance

March 21, 2017

Author: David Kanter

AMD’s upcoming Naples server processor scales to two sockets and packs up to 32 Zen CPU cores with 64 threads, eight DDR4 memory channels, and an impressive 128 PCIe 3.0 lanes in each package. It’s the reincarnation of the company’s server line, which was ground into obscurity by poor architectural and implementation decisions along with Intel’s relentless execution over the past decade. AMD is targeting one- and two-socket servers, which constitute most of the market. The Naples family is scheduled to enter production in 2Q17 and is now sampling to customers. The company already has a prominent design win in Microsoft’s Project Olympus platform, which will serve in Azure’s infrastructure.

To support its 32 cores, Naples integrates 16MB of L2 and 64MB of L3 cache. We expect each core will deliver 5–15% lower IPC than Intel’s current Skylake CPU on integer workloads. The Zen cores may have an advantage on SSE code and cryptography, courtesy of additional execution units. The memory controller drives eight DDR4 channels at 2.67GT/s for a total bandwidth of 171GB/s, and it supports up to two registered ECC DIMMs per channel with a maximum capacity of 2TB per socket. By contrast, Skylake-EP will probably offer no more than six channels, lagging in bandwidth and capacity.

In a single-socket system, Naples offers an impressive 128 PCIe 3.0 lanes for GPUs, storage, and networking. To create a dual-socket system, 64 of the PCIe lanes are configured to carry coherent traffic between sockets, leaving 64 lanes for I/O in each socket. The coherent links have a raw throughput of 63GB/s in each direction, but the usable data rate is lower because of packet overhead. As a result of this approach, one- and two-socket systems have the same I/O capabilities and only scale the memory and core count. 

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