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Arteris Ncore 2.0 Simplifies Safety

April 25, 2017

Author: Loyd Case

The Arteris Ncore 2.0 network-on-a-chip (NoC) gives developers of machine-learning SoCs for autonomous vehicles an easy way to implement safety standards. The major addition is Ncore Resilience, which automatically incorporates ISO 26262 requirements in a chip design. Other features include non-power-of-two agent support, low-latency proxy caches, and new coherent-memory-cache intellectual property (IP). Announced at the recent Linley Autonomous Hardware Conference, Ncore 2.0 RTL is available now.

The original Ncore was a major update to the Arteris NoC portfolio, offering cache coherence. It also allowed designers to add proxy caches, enabling noncoherent agents to more easily share data with coherent agents and with other noncoherent agents. The company designed Ncore 2.0 with an eye toward the emerging generation of machine-learning processors, which often employ different types of accelerators. Most new machine-learning accelerators target automotive systems that must adhere to the ISO 26262 safety standard. The Arteris Resilience add-on eases implementation of safety-critical features in SoCs.

Resilience also implements a fault controller that monitors and manages fault detection. This controller consists of RTL for a state machine that can be dropped into the design to handle fault identification and self-testing. The NoC offers parity protection for the data path and ECC protection for all on-chip memories, including the proxy cache. The Ncore smart duplication feature avoids duplicating protected links and memories; it only duplicates agents that directly affect data packets. The fault controller comes with built-in self-test (BIST) to ensure it remains uncorrupted.

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