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Intel Sets Tiny 10nm Goal Posts

April 25, 2017

Author: David Kanter

Manufacturing is the forte and pride of Intel, which is widely considered to be the best in the semiconductor industry. But at the most recent node, the company stumbled with yield problems and a slow ramp, then it admitted to delays in its 10nm development. Intel recently disclosed a significant amount of information about the current 14nm and forthcoming 10nm processes, although it continues to withhold many technical details. This disclosure, despite being selective, reaffirms the company’s technology leadership and clarifies its manufacturing strategy by showcasing the superior density and performance of its 10nm process. That process is scheduled to enter production in late 2017.

Intel acknowledged that the foundries’ 10nm node is slightly denser than its 14nm technology. But it also described 14+ and 14++ variants that boost transistor performance by 12–25%, enabling continuous product improvements during its 10nm delay. These improvements help Intel match the performance (but not the density) of foundry 10nm technologies that are in or near production.

At the same time, the company directly challenged competitors’ marketing by disclosing select data for its 10nm technology, which is far denser than the foundries’ 10nm. In this new node, Intel continues to scale using ever taller FinFETs and self-aligned quadruple patterning for metal interconnects. Moreover, the 10nm process employs a new contact that sits above the transistor and reduces isolation spacing for standard cells, boosting density by an additional 20–30%. The result is a process that reduces the die area of a hypothetical microprocessor by an impressive 57%. The superior scaling somewhat compensates for the slower three-year node transition, although only the later 10nm iterations (10+ in 2018 and 10++ in 2019) will boost transistor performance beyond the 14++ level.

Subscribers can view the full article in the Microprocessor Report.

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