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Andes NX25 Takes a RISC-V

May 16, 2017

Author: Loyd Case

The momentum for RISC-V is accelerating, as Taiwan-based Andes Technology has adopted the BSD-licensed instruction-set architecture (ISA) as the core of its next-generation AndeStar V5. Andes is the first established vendor of CPU intellectual property (IP) to offer a RISC-V core for licensing. The AndeStar V5 ISA combines the compact base RISC-V instruction set, comprising roughly 60 instructions, with Andes-specific extensions. Like V3, the new V5 will have over 150 instructions when using all extensions. Its first implementation will be the NX25 CPU IP, slated for RTL release next quarter. The company sees networking, storage, and machine-learning accelerators as targets for the 64-bit NX25; all need more than 4GB of address space.

Andes designs low-power CPU cores that are well suited to a range of applications from low-cost embedded SoCs to advanced data-center chips. Most of its customers are in Asia, but it has achieved a noticeable presence in other markets since 2015. The company licenses all of its CPU designs as IP cores and has license agreements with 120 different companies for communications, security, IoT, machine-learning accelerators, and consumer applications. More than two billion chips using Andes cores have shipped.

RISC-V is general-purpose ISA that’s BSD licensed, extensible, and royalty free. Unlike GPL-based open-source licenses, BSD doesn’t require source-code distribution, making it a better choice for companies that wish to design commercial products using RISC-V. In addition, several RISC-V CPU cores are available as open-source RTL. Most were developed at universities—including UC Berkeley, where RISC-V first emerged. SiFive recently announced plans to license RISC-V cores, but the startup has no track record as an IP vendor.

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