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Cadence C5 Flexes for Neural Networks

May 30, 2017

Author: David Kanter

Enlarging the Tensilica Vision DSP IP family, Cadence’s new C5 focuses on convolutional neural networks (CNNs) and can execute more than one trillion 8-bit multiply-accumulate (MAC) operations per second when implemented in TSMC 16FF+ technology. The DSP requires less than 1mm2 in this technology. The company is currently working with early licensees; the first processors using the C5 could enter production by the end of 2018. These initial products are likely to target automotive vision/radar/lidar, drones, surveillance, and mobile applications.

The Vision C5 employs the same base DSP architecture as the Vision P5 and P6, but it adapts that architecture for neural networks rather than imaging. Cadence removed many imaging features while adding wider SIMD and CNN-specific instructions and hardware. Augmenting the DSP to accelerate CNNs enables it to handle mixed workloads, improving both programmability and power efficiency.

To boost raw compute performance, the new C5 focuses on specific SIMD MAC operations to provide greater throughput than its brethren. The company removed floating-point (FP) support, which is optional in the P6 and unnecessary for most neural-network inferencing. It also eliminated 8x16 MAC operations. In exchange, the C5 has quadruple the number of MAC units compared with the P6 and can sustain 1,024x 8x8 MACs. For 16x16 MACs, it has 8x the throughput of the P6, delivering 512 of these operations.

The cumulative result of these changes is that the C5 offers 3.5–4.0x better performance than the P6 (depending on the implementation) on AlexNet, Inception, and other CNNs. This boost comes at the cost of greater specialization, though. For combined imaging and neural-network applications, Cadence recommends the P6, but the C5 is a great option for customers that want the best CNN performance.

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