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Cortex-A75 Has DynamIQ Debut

May 30, 2017

Author: Linley Gwennap

Just a year after rolling out Cortex-A73, ARM has delivered a new high-performance CPU branded Cortex-A75. The A75 delivers 22% more integer performance than the A73 in the same mobile power envelope, according to the company’s estimates, making it ideal for next-generation premium smartphones. Yet it runs even faster using the greater thermal capacity in embedded systems, and it includes reliability features that the A73 lacks, making it well suited to infrastructure equipment, too.

Cortex-A75 boosts performance using a long list of microarchitecture improvements over the A73, but most importantly, ARM widened the instruction-fetch unit to four per cycle and added a third decoder. Although these two changes provide the biggest gains in instructions per cycle (IPC), additional tweaks in branch prediction, prefetching, instruction-issue queues, and the memory subsystem also contribute. A faster FMAC unit raises floating-point scores.

Further gains come from a new cluster architecture that ARM calls DynamIQ. This design gives each CPU its own private L2 cache while all CPUs in the cluster share an L3 cache. The private L2 halves the response time compared with the older shared L2, accelerating memory-intensive applications. The new design also allows for mixing of different CPU types in a single cluster. So far, however, the only cores that support DynamIQ (and therefore mixing within a cluster) are Cortex-A75 and its new little brother, Cortex-A55. These are also the first two Cortex CPUs to support the ARMv8.2 extensions.

Production RTL for the A75 and A55 is now available to lead customers. Mobile processors using the new cores are expected to enter production late this year, and these designs should be prevalent in premium and mid-tier smartphones in 2018. Embedded processors based on the A75 and A55 will take longer to reach the market but should enter production in 2018.

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