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SiFive Begins Licensing Cores

June 6, 2017

Author: Jag Bolaria

SiFive began as a supplier of RISC-V ASICs and now offers two licensable CPU cores as well. Specifically, its Coreplex E-series targets traditional microcontrollers, and the Coreplex U-series targets 64-bit embedded SoCs and processors. The company released the E-series RTL in 1Q17 and plans to offer the U-series RTL by the end of 2017. The new business model helped it raise $8.5 million in Series B funding from Osage University Partners, Spark Capital, and existing investor Sutter Hill Ventures.

The synthesizable E51 Coreplex is a 64-bit single-issue CPU that executes one instruction per clock cycle and has a five-stage in-order pipeline. It implements branch prediction using a 40-entry branch target buffer, a 128-entry branch history table, and a 2-entry return address stack. The CPU lacks a floating-point unit as well as an MMU, precluding compatibility with Linux and other high-level operating systems (HLOSs). The E31 Coreplex is a smaller 32-bit implementation. It has the same pipeline, cache, and interrupt structure as the E51, but the registers and data path are only 32 bits wide.

SiFive and the RISC-V Foundation want to make CPU intellectual property (IP) less expensive and easier to license. Customers can freely download and evaluate a product and quickly purchase it with few legal constraints. In the near term, SiFive’s best opportunity for the E-series will be the E31, as the E51 lacks HLOS capability, making it uncompetitive. Once a few small licensees of SiFive IP begin shipping products, the company will have a better opportunity to win larger accounts, but doing so will take several years and require more funding.

Subscribers can view the full article in the Microprocessor Report.

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