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MIPS I6500-F Drives Functional Safety

July 4, 2017

Author: Loyd Case

Imagination has added safety enhancements to its MIPS I6500 CPU intellectual property (IP). The new version, dubbed the I6500-F, targets safety-conscious markets such as autonomous driving, commercial drones, and industrial systems. It adds support for logic built-in self-test (LBIST), I/O parity, and core timeout functions to ease adherence to ISO26262 and other functional-safety standards. Mobileye has adopted the I6500-F for its next-generation EyeQ5 autonomous-driving processor. The new core is available for licensing now; production RTL should be generally available later this year.

Functional safety has become a hot topic as chip vendors rush into self-driving cars, autonomous drones, and other new markets. Automotive systems must adhere to ISO 26262 and its associated Automotive Safety Integrity Levels (ASILs) B through D. Other standards, such as IEC 61508, cover industrial functional safety. These standards mandate robust error detection and mitigation to ensure a vehicle continues to operate safely even after a component failure.

Imagination first delivered the I6500 late last year. That MIPS Release 6 CPU provides 64-bit capability, simultaneous multithreading (SMT), and support for clusters of up to six cores and two I/O-control units (IOCUs). A fully cache-coherent design, it can share its L2 cache with other clustered CPU cores as well as with external coherent accelerators. The I6500 uses cache coherence plus low latency through its IOCUs to boost throughput when communicating with dedicated accelerators, including the latest neural-network accelerators.

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