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Cypress PSoC 6 Broadens MCU Lineup

July 4, 2017

Author: Loyd Case

Cypress has taken a “more is better” approach to its latest IoT-focused MCUs: the PSoC 6 portfolio now includes more memory, more storage, more I/O, and an additional Cortex-M4 CPU dedicated to application processing. The company revealed details of two PSoC 6 models, the PSoC 62 performance and PSoC 63 connectivity MCUs. It plans to deliver future lineups that address motor control, entry-level processing, and human/machine interfaces (HMIs). Cypress began sampling the new MCUs in 2Q17; volume production is slated for 4Q17.

The PSoC 6 family incorporates 32-bit ARM Cortex-M4 cores and comprises five product segments. The PSoC 60 Value Line and PSoC 61 Programmable Line have only one ARM Cortex-M4F, which is suitable for simple low-cost systems. The PSoC 60 lacks a built-in cryptography coprocessor. The PSoC 62, PSoC 63, and PSoC 65 employ a dual-core architecture based on ARM’s Cortex-M4 and Cortex-M0+ CPUs. The PSoC 62 targets more-performance-intensive tasks that need extensive I/O and HMIs. The PSoC 63 Connectivity Line adds Bluetooth 5 for wearables and other wireless devices. Finally, the PSoC 65 Motor Control Line, as the name implies, targets advanced motor controls.

PSoC 6 MCUs with dual cores employ the Cortex-M4 to run applications while the Cortex-M0+ acts as an offload engine for auxiliary tasks. The architecture builds in hardware-based security features such as a trusted execution environment (TEE), which is rare in this MCU class. The PSoC 65 uses the M0+ to manage digital I/O, including digital-sensor monitoring, while the M4 handles analog I/O and runs applications. 

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