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Skylake-SP Scales Server Systems

July 18, 2017

Author: David Kanter

Over the last 25 years, Intel has gradually shifted from reusing client processors in the data center to designing server-centric platforms. The new Purley platform and 14nm+ Skylake-SP processor are the final stage of this evolution, as they fully differentiate server processors from client processors. Instead of simply reusing the client CPU and extending the client ring fabric to greater core counts, Intel extensively modified the CPU to boost performance on server workloads.

The Skylake-SP CPU core clearly descends from the Skylake client core, but it boasts a larger 1MB L2 cache and AVX-512 support, including 512-bit-wide vector units. The new on-die mesh fabric no longer resembles the lower-bandwidth client ring fabric, and the L3 cache is noninclusive with smaller 1.375MB slices. Similarly, the memory and I/O controllers provide greater performance and connectivity. Skylake-SP also has the new Ultra Path Interconnect (UPI), a coherent system interface that’s faster and more efficient than the client’s Quick Path Interconnect (QPI). The server processor targets 70–205W TDPs, barely overlapping those of PC processors.

Living up to its name, Intel is integrating more pieces of the system architecture. Like Xeon Phi, Skylake-SP offers in-package Omni-Path adapters for high-performance computing (HPC). In addition, the Lewisburg south-bridge chipset (PCH) has several 10G Ethernet (10GbE) and Non-Volatile Memory Express (NVMe) controllers. At the same time, Skylake-SP will bring heterogeneous computing to mainstream servers. Intel can integrate accelerators such as FPGAs and Nervana neural-network accelerators in the processor package, and the south bridge comes with dedicated cryptography and compression hardware.

Skylake-SP is designed for a range of server tasks, including cloud services, enterprise applications, HPC, storage, and networking. It covers a wide range in performance, power, and price. Furthermore, the new platform delivers a substantial performance boost without requiring a process shrink to increase transistor density.

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