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RISC-V U54 Runs Linux

October 10, 2017

Author: Linley Gwennap

SiFive continues to roll out new CPUs, this time delivering its first core with a full memory-management unit (MMU) for Linux and other high-level operating systems. Like its previous cores, the U54 employs a simple five-stage in-order pipeline that can execute a single instruction per cycle. The new MMU allows the company to target low-performance embedded systems that require a full OS, such as smart TVs, broadband gateways, and IoT hubs. Introduced at this month’s Linley Processor Conference, the U54 recently taped out; production RTL will be available to customers by the end of the year.

SiFive also disclosed a new “coreplex” that packs four U54 CPUs plus a management CPU based on its E51 design. This design is the company’s first to include multicore support and cache coherence. Each of the main CPUs features 32KB of instruction cache and 32KB of data cache, and they share a coherent 2MB level-two cache. The company will license the CPU and coreplex to SoC and ASIC designers; although the RISC-V instruction set and CPU generator are open source, customers must pay to license a complete, validated, and supported core design. SiFive will develop complete chips for customers as part of its ASIC-design program, too.

The U54 is based on the same basic pipeline as SiFive’s other cores, which originate from the Rocket CPU generator that the company’s founders developed while at UC Berkeley. All integer instructions use a five-stage pipeline that’s similar to early RISC designs. This short pipeline minimizes penalties for mispredicted branches and other hazards. Keeping the design simple reduces die area as well. In general, however, shorter pipelines operate at lower clock speeds, and this design will be limited by its single-cycle cache accesses. SiFive expects the U54 to reach 1.5GHz in TSMC’s 28nm HPC technology.

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