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NetSpeed Applies AI to SoC Design

October 17, 2017

Author: Linley Gwennap

Chips are using artificial intelligence to get smarter, so why shouldn’t chip designers? NetSpeed’s new Turing system applies machine learning to help designers improve their next-generation SoCs. The company has enhanced its network-on-a-chip (NoC) design tools to better optimize the on-chip interconnect by applying lessons learned from dozens of previous SoC designs. The more customers use Turing, the smarter it gets.

Users begin by entering their design requirements, listing the various intellectual-property (IP) blocks, their performance requirements, basic connectivity (what connects to what), and some example workloads or use cases. Turing then taps its machine-learning algorithms to analyze the requirements and create several alternative NoC configurations. It then evaluates each alternative for performance, power, and die area (PPA) in each use case, identifying a few design options that deliver the best PPA. The chip designer can then review and select one of these options, or fine-tune the requirements to generate another round of choices.

Although Turing is based on machine learning, it can be applied to any SoC design, whether that SoC implements a neural engine or not. Neural engines are just one of several hardware accelerators that make modern SoCs more complex than ever. NetSpeed’s new tool is like having a guru architect on call to provide design advice. Processor architects can take Turing’s advice and then devote their time to solving the other hard problems in their SoC design.

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