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Ncore 3.0 Flexes Interface Chops

October 17, 2017

Author: Loyd Case

ArterisIP is continuing a steady pace of updates to its Ncore intellectual property (IP) for coherent network-on-a-chip (NoC) interconnects, adding Ace, Chi, and CCIX interoperability. Ncore 3.0 also adds optimizations that enable designers to target a 2.0GHz clock frequency in 16nm designs. This latest version, announced at the recent Linley Processor Conference, has been available to a few early customers; wide release is slated for 2Q18.

ArterisIP (formerly called Arteris) delivered the first Ncore NoC IP in 2016, offering coherent-interconnect capability for the first time. It followed in April of this year by adding its Resilience package, which brings optional IP and tools that allow Ncore users to more easily meet ISO 26262 safety requirements. Resilience targets autonomous-driving ASICs that combine CPUs, GPUs, and other heterogeneous but coherent cores.

Arm’s Chi is a coherent fabric that often serves in Cortex-based multicore processors. The CCIX standard effectively extends Chi to handle coherent chip-to-chip connections, so ArterisIP enabled it in its latest IP. Ncore 3.0 works with CCIX coherent agents that link to the external CCIX PHY and controllers, converting CCIX protocols to its internal NoC protocols.

The new IP also enables SoC designers to integrate Ace coherent interfaces. When communicating with noncoherent agents using Amba AXI or Ace-Lite, Ncore’s proxy cache allows those agents to participate in the coherent system. As with the CCIX-agent interface, the Ace agent converts Ace protocols to internal protocols.

Ncore 3.0 allows ArterisIP customers to more easily integrate third-party agents created for other interconnect technologies. Since many of these customers design their own secondary processors or hardware accelerators that must coexist with host processors based on other interconnects, the new design makes life much easier.

Subscribers can view the full article in the Microprocessor Report.

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