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UltraSoC Embeds Run-Time Analytics

October 17, 2017

Author: Mike Demler

UltraSoC Technologies develops licensable intellectual property (IP) for analyzing and monitoring a chip’s internal operations. The IP includes traditional test-bench debug functions that engineers use to bring up devices before production, but it also offers capabilities for in-field run-time data logging and reporting, performance optimization, and security monitoring.

The UltraSoC hardware works with a variety of CPU/GPU/DSP architectures and other types of IP cores, as well as with custom logic. One component is a USB2.0 debug communicator module, which offers a higher-speed alternative to a JTAG port. The interfaces to the analysis and monitoring module are compatible with standard or proprietary on-chip interconnects as well as with third-party networks-on-a-chip (NoCs). The UltraSoC components, however, connect together on a separate message-passing infrastructure without using any of the underlying SoC resources.

Designers integrate the configurable and synthesizable UltraSoC RTL components with their chip architecture during SoC implementation, but users can configure and change the IP’s functions at run time. The analytics and debug IP modules are nonintrusive, connecting passively to master and slave system-bus interfaces to sniff data traffic in the various logic blocks. Configurations vary, but on average, the analytics functions and messaging infrastructure add approximately one percent to the die area, according to the company’s calculations.

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