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FPGAs Accelerate Deep Learning

November 21, 2017

Author: Linley Gwennap

Nvidia GPUs are the most popular chips for accelerating deep learning, but some large cloud-service providers (CSPs) are getting better results using FPGAs. For example, Microsoft has deployed FPGAs across its data centers, where they can accelerate its deep-learning algorithms using its Brainwave project. Other CSPs such as Amazon and Baidu also employ this approach for some of their deep neural networks (DNNs). DeePhi, TeraDeep, and other startups offer preprogrammed FPGA accelerators for DNNs. These accelerators mainly target neural-network inferencing, as GPUs dominate the training function.

The FPGA’s flexibility is well suited to deep learning, a relatively new field that’s developing quickly. Researchers continue to revise DNN algorithms, convolution functions, and data formats. As CSPs gain more experience with their DNN workloads, they discover new optimizations. FPGAs can be reprogrammed in minutes, whereas conventional hardware designs take months or even years to update.

Although some people think of FPGAs as a pile of unstructured gates, these devices also include a set of “hard” features designed directly into the silicon. In addition to basic memory and register blocks, most FPGAs feature hard DSP blocks, because their customers frequently perform signal processing. These DSP blocks are much denser and operate at a higher speed than similar compute blocks constructed from programmable gates. They’re usually configurable for either integer or floating-point calculations.

These DSP blocks offload the multiply-accumulate (MAC) function critical to many DNN algorithms. Some FPGAs have thousands of DSP blocks, generating a huge amount of compute power. Unleashing this performance, however, requires custom gate-level design, a specialized and time-consuming task. Both Intel (formerly Altera) and Xilinx offer tools to ease this burden.

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