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Open-Silicon IP Targets Networking

December 12, 2017

Author: Bob Wheeler

Better known as an ASIC vendor, Open-Silicon is expanding its intellectual-property (IP) portfolio. Building on its existing Interlaken core, the company announced IP cores for the Ethernet physical coding sublayer (PCS), for forward error correction (FEC), and for Flex Ethernet (FlexE). It also upgraded its Interlaken core to handle interfaces up to 1.2Tbps. The cores are available now for licensing or for use in new ASIC designs.

The company’s new PCS core handles Ethernet rates from 10Gbps to 400Gbps including the new 25Gbps, 50Gbps, and 200Gbps speeds. It performs multilane distribution (MLD), 64/66b encoding, scrambling, alignment-marker insertion/removal, and other functions between the MAC layer and the FEC interface. The new multichannel multirate (MCMR) FEC core supports both Ethernet and Interlaken. It handles Reed-Solomon FEC codes for various 802.3 clauses including the KP4 and KR4 variants of 802.3bj.

Open-Silicon’s new FlexE core is an optional block that logically sits between the Ethernet MACs and the PCS layer. FlexE is an Optical Internetworking Forum (OIF) specification that allows more-granular Ethernet link rates. The FlexE core is essentially a sophisticated multiplexer (or gearbox) that handles MAC rates from 10Gbps to 400Gbps and adapts them to 100Gbps PCS lanes.

The latest Interlaken core is what Open-Silicon calls its eighth-generation design. Enhancements include support for 56Gbps serdes rates, interfaces up to 1.2Tbps, and optional FEC (using the MCMR FEC core). The Interlaken Alliance specified optional Reed-Solomon FEC in an extension published in December 2016.

With its new Interlaken, FlexE, and FEC cores, Open-Silicon is providing IP that isn’t widely available from third parties. Also, it can customize these blocks to meet the specific requirements of customer designs. The expanded networking IP benefits customers by allowing them to focus on product differentiation rather than “recreating the wheel” by implementing standard blocks.

Subscribers can view the full article in the Microprocessor Report.

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