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Gyrfalcon Shrinks AI Accelerator

February 20, 2018

Author: Linley Gwennap

A year ago, you may have resolved to lose a few pounds, but Kimble Dong, Frank Lin, and Lin Yang had a more ambitious resolution. In January 2017, they founded Gyrfalcon with a goal of developing the most power-efficient neural-network accelerator chip and demonstrating it at CES—in a single year. The team not only met this goal but also signed several customers, including a top-five smartphone maker. The design, branded Lightspeeur, is now ready for production and available as a chip or in a USB stick.

To get to market so quickly, the company chose a simple design based on Yang’s PhD research at UC Berkeley, which proposed a matrix architecture for neural networks. Taking advantage of this approach, the Lightspeeur 2801 contains more than 28,000 MAC units plus nearly 9MB of SRAM, enabling it to operate without external memory. At its peak speed of 100MHz, the chip delivers 5.6 trillion operations per second (TOPS). At 50MHz, it uses just 300mW (typical), yielding an incredible power efficiency of 9.6 TOPS/W. Having little circuitry other than the memory and MAC units, the 2801 functions as a coprocessor, offloading most CNN layers from the host processor.

The Gyrfalcon chip targets inference applications, not training. It implements a proprietary 9-bit floating-point format (FP9) to simplify the MAC units while maintaining accuracy for most CNN implementations. The 2801 can handle difficult problems such as speech recognition, image recognition, and natural-language processing while fitting in the power and cost budget of a smartphone or other consumer device. It can also serve in industrial and even data-center systems.

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