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Arteris IP Offers Last-Level Cache

June 26, 2018

Author: Mike Demler

Expanding its portfolio, network-on-a-chip (NoC) supplier Arteris IP now licenses a last-level cache (LLC) it calls CodaCache. The new intellectual property (IP) enables designers to boost performance by connecting processor blocks to on-chip caches integrating up to 8MB of dedicated or shared storage per instance. Inserting the caches between the function blocks and external memory can ameliorate access bottlenecks, reducing latency as well as power. The CodaCache LLC is also configurable as scratchpad memory.

Whereas the company’s Ncore NoCs include proxy caches that support coherent block-to-block operations, CodaCache is a standalone product that accelerates chips integrating multiple noncoherent blocks. It can attach directly to an SoC interconnect through the built-in AXI4 master/slave interfaces or to the company’s noncoherent FlexNoC interconnect.

The ability to add the caches directly to the SoC bus lets designers improve performance and power when reusing processor architectures. The CodaCache architecture allows connection of multiple instances; designers can therefore dedicate some to accelerate particular IP blocks, as well as integrate more than 8MB total. Multiple instances can also ease physical placement. Since each LLC has one set of master/slave AXI interfaces, using several LLCs increases the total number of cache-access ports, boosting overall system performance.

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