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Xilinx Everest Outclimbs FPGAs

September 11, 2018

Author: Tom R. Halfhill

Xilinx is redefining FPGAs with its next-generation Everest family. Instead of marketing them as FPGAs with embedded CPU cores, the company is pitching them as full-fledged SoCs augmented with programmable logic. They upend the traditional orientation of FPGAs by surrounding the programmable gates with more of everything: processing cores, hard logic, fast interconnects, and I/O interfaces. The new heterogeneous chip architecture—which Xilinx calls an adaptive compute acceleration platform (ACAP)—can boot and run as an SoC even without configuring the gates.

At the recent Hot Chips conference, Xilinx focused on one new aspect: hardened compute cores tentatively called hardware/software programmable engines (PEs). An official name is coming at the Xilinx Developer Forum in October, when the company plans to announce more product details. Scheduled to tape out this year, Everest chips will be built in 7nm FinFET technology at TSMC. We estimate they’ll begin volume production in 2H19 or 1H20, when they’ll supersede today’s 16nm UltraScale+ FPGAs as the new midrange and high-end models.

Everest will integrate tens to hundreds of the new PEs with Arm Cortex-A cores and other UltraScale+ features. We expect an upgrade from UltraScale’s Cortex-A53 to newer, more powerful Arm CPUs. Other feature additions include hard-logic DRAM controllers with error correction (ECC), 112Gbps serdes, and PCI Express Gen4 controllers. The programmable logic will range from hundreds of thousands of logic cells to more than 10 million cells. Some models will add extensive analog logic, replacing current UltraScale+ RFSoCs.

Xilinx hopes Everest will replace some conventional SoCs, ASICs, and ASSPs in addition to upgrading designs that employ current FPGAs. In particular, it’s pursuing three fast-growth markets: data centers, 5G cellular networks, and autonomous vehicles. Everest retains and enhances the features expected of FPGAs, offering greater compute performance, faster signal processing, higher I/O throughput, and larger gate counts.

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