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AIware3 Adds Rings to Neural Engine

November 6, 2018

Author: Mike Demler

AImotive announced AIware3, its third-generation licensable engine for autonomous-vehicle neural networks, at the recent Linley Processor Conference. It left most of AIware’s core architecture unchanged, but to enable higher performance, it developed a new configurable ring structure that connects multiple compute units. Each ring comprises a set of 512- to 1,024-bit synchronous lanes, which can scale to 80 trillion bits per second—sufficient to support 10 trillion multiply-accumulate operations per second (TMAC/s) at INT8 resolution. A ring can have its own gateway to external memory as well as to other rings. The design allows connection of up to eight rings on a chip with an inter-ring arbiter, thereby preventing conflicts when sending data to or from shared I/O ports. The company plans to release production AIware3 RTL in 1Q19.

Although many intellectual-property (IP) vendors are racing to deliver neural-network accelerators for autonomous vehicles, AImotive is unique owing to its complete automotive-software stack and simulation tools. Customers use AIdrive software for self-parking and highway autopilot, and in 1H19, the company plans to release software for urban self-driving. It also offers AIsim for AI-system testing and training in a realistic visual environment.

Although AIware3 targets 7nm automotive chips, it will compete with licensable cores from a long list of experienced IP vendors, including automotive specialist Videantis as well as Cadence, Ceva, and Synopsys. AImotive lacks the scale and support network to compete with those companies, but the combination of AIware3, AIdrive, and AIsim offers OEMs and autonomous-driving startups a more complete hardware/software solution for their custom ASICs.

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