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New MCUs Embrace Cortex-M33

December 18, 2018

Author: Tom R. Halfhill

NXP and STMicroelectronics are sampling the first microcontrollers to use Arm’s Cortex-M33, which adds TrustZone security to the 32-bit Arm v8-M architecture. Designed for embedded systems that need higher security than conventional MCUs can promise, these chips separate bootstrap loaders, operating systems, and application programs into trusted or untrusted partitions, privileged or not. Additional security features include secure boot, cryptography acceleration, true-random-number generators, tamper detection, and encrypted memory.

Task isolation is the signature feature of the Arm v8-M instruction-set architecture (ISA), which Arm introduced two years ago. The ISA’s baseline subprofile echoes Arm v7-M by adding mutually exclusive access for shared memory in multicore processors, among other features. The mainline subprofile adds an optional 32-bit FPU, DSP extensions, and a coprocessor interface.

NXP’s new LPC5500 family includes some dual-core models, whereas ST’s new STM32L5 family includes single-core models. But the dual-core NXP parts have only one core that implements the mainline subprofile with TrustZone and other Cortex-M33 optional features. The second core is a baseline coprocessor that offloads untrusted and unprivileged tasks from the main CPU. Both companies target consumer, commercial, and industrial systems as well as IoT devices, although these chips lack integrated radios.

As usual for MCU vendors, NXP and ST will offer their new products in numerous variations with multiple memory-size, I/O, and package options. Only the superset models began sampling this quarter; others will sample throughout 2019. ST is scheduling production for 2Q19, and we expect NXP to begin production in 2H19.

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