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WD Rolls Its Own RISC-V Core

February 5, 2019

Author: Bob Wheeler

Storage vendor Western Digital (WD) has declared independence from licensed CPUs by designing its own RISC-V core. SSD controllers are the first application for its new Swerv EH1 RISC-V CPU. Flash-based products now represent about half its revenue, and WD designs both 3D NAND chips and associated controllers. Over the next several years, it plans to move most of its controller shipments—representing more than one billion CPUs—from licensed to in-house designs. The company has also made the Swerv design available as open source.

Owing to its target application, WD designed the Swerv EH1 as a simple 32-bit real-time core that offers relatively high performance. It implements only the RV32I base ISA plus the multiply and divide (M) and compressed (C) extensions. Its dual-issue in-order pipeline delivers a competitive 5.0 CoreMarks per megahertz. WD completes the core with an instruction cache, tightly coupled memories (TCMs) for instructions and data, an interrupt controller, a debug block, and four 64-bit AXI buses for memory and I/O. Although it aimed for 1.0GHz worst-case operation in TSMC 28nm technology, it achieved 1.8GHz operation in a typical process corner.

The Swerv EH1 is similar to SiFive’s new E76 CPU, which achieves slightly lower clock speeds and CoreMarks per megahertz. Last April, WD announced an investment and multiyear license agreement with SiFive, but Swerv is separate from that agreement. Instead, the two companies independently developed dual-issue RISC-V CPUs. Owning Swerv gives WD maximum control over deeply embedded designs. At the same time, it can use third-party RISC-V CPUs or processors (chips) for higher-end products such as storage systems.

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