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Intel 10nm FPGAs Add Chiplets

April 9, 2019

Author: Tom R. Halfhill

Intel’s next-generation Agilex FPGAs diverge from Xilinx’s new Versal devices in important ways. Although both companies want to expand the FPGA market by augmenting their programmable logic with faster processing and I/O, Intel favors multichip packages tailored for particular applications or customized for special customers. Xilinx, which disclosed its Versal family last year, favors more chip-level integration and preconfigured product tiers. Both vendors plan to sample their new devices later this year and begin volume shipments in 2020.

Agilex (code-named Falcon Mesa) is Intel’s first new FPGA family since acquiring Altera in 2015. Enough time has elapsed since the $16.1 billion acquisition—Intel’s most expensive—to forge a new strategy that counters Xilinx and exploits the strengths of the merged companies. Although product details remain sketchy, the strategy is clear. Intel will use its new 10nm FinFET process and copackaging technology to build FPGAs that combine a programmable-logic chip with one or more chiplets. Some Stratix FPGAs and x86 processors already employ this packaging technology, but Agilex expands it and allows customers to develop their own chiplets.

Chiplets can add high-speed transceivers, memory-coherent host-processor interfaces, PCI Express interfaces, or custom logic. Intel will offer chiplets with 112Gbps serdes, PCIe Gen5, High Bandwidth Memory (HBM), and 3D XPoint memory controllers. Its 2018 acquisition of eASIC allows customers to harden part of their programmable-logic design into a tightly coupled chiplet that delivers higher performance and power efficiency.

Thanks largely to the process shrink from 14nm to 10nm, Intel says Agilex will deliver up to 40% more performance than existing Stratix 10 FPGAs or consume up to 40% less power. Peak floating-point performance soars to 40Tflop/s. Sampling is scheduled for 3Q19, although we expect the company will roll out the entire product family over several quarters.

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