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Andes Strengthens Its RISC-V Arsenal

April 16, 2019

Author: Mike Demler

Andes has upgraded its A25 and AX25 RISC-V CPUs, adding cache-coherent multicore support in the new MP models along with an optional DSP extension. The designs implement the AndeStar V5 ISA, which is a superset of RISC-V. The A25 is compatible with RISC-V’s 32-bit RV32 ISA, and the 64-bit AX25 is compatible with RV64. They employ the same architecture as the company’s N25 and NX25, respectively, but add an MMU to run Linux.

The new multicore option allows customers to integrate the A25MP and AX25MP in cache-coherent clusters of two or four cores. In 28HPC+ technology, the CPUs can run SMP Linux at over 1.2GHz, but the worst-case specification is 1.0GHz.

Andes chairs the RISC-V Foundation’s Packed-SIMD DSP (P-DSP) task group. It contributed the AndeStar V3 DSP extension as the starting point for that standardization effort. Previously, it offered the DSP extension in the N10/D10, N15/D15, and other V3 CPUs. The DSP ISA only uses general-purpose registers (GPRs), reducing its area impact. Task-group members are reviewing the proposal, but the A25MP and AX25MP already support it. Andes also uses the P-DSP draft ISA in the new standalone 32-bit D25F, an A25 core without an MMU, targeting DSP applications that don’t need Linux.

Along with the new multicore CPUs, the company rolled out the tiny N22. This model is compatible with the RV32C ISA, which includes a compressed 16-bit-instruction subset. It’s a two-stage CPU that designers can implement in as few as 15,000 gates. Optimized for performance, the N22 runs at 800MHz in a 28HPC+ process. The D22F version adds DSP extensions and an FPU.

Subscribers can view the full article in the Microprocessor Report.

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