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Flex Logix Moves Into Chips

April 16, 2019

Author: Mike Demler

After four years of creating embedded-FPGA intellectual-property (IP) cores, Flex Logix is entering the AI-chip business. The InferX X1 is an AI coprocessor designed to connect to a host CPU through its PCIe interface. The new chip integrates four enhanced versions of the NNMax tiles the company introduced last year in an IP core. The company will continue licensing FPGA IP and will selectively license the NNMax IP, but it expects InferX chips and boards to quickly become its largest revenue source. It plans to manufacture the X1 in 16FFC technology at TSMC and to ship samples around the end of the year, making production likely in late 2020.

The InferX X1 targets edge gateways, low-end servers, robotics, surveillance cameras, and other high-performance edge devices. The company plans to sell it in a chip package as well as on a half-height half-length PCIe card and a full-height half-length card containing two chips. The X1 has a four-lane PCIe Gen3/4 interface; it also has 32 GPIO ports, allowing it to connect to MCUs that lack PCIe. The GPIO ports additionally enable customers to connect two or four chips in parallel.

Although Flex won’t tape out the X1 until 3Q19, it has run cycle-accurate gate-level simulations. For a fast-fast process corner in a device operating at maximum temperature and voltage while running Yolo v3, the simulations predict 7.1W for worst-case power consumption. Running the less complex ResNet-50, typical power consumption falls to 2.2W. At a 1.0GHz clock rate, the four-tile chip delivers approximately 8.5 trillion operations per second (TOPS). By comparison, the ResNet performance per watt is 9x that of NovuMind’s NovuTensor, which also works as a PCIe-connected AI coprocessor.

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