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Wave to License TritonAI IP

April 23, 2019

Author: Mike Demler

Wave Computing assembled its new TritonAI-64 intellectual-property (IP) platform from three components. They include a modified version of the compute cluster from its data-flow processors (DPUs), which it now calls a WaveFlow cluster; a new WaveTensor compute tile; and a new MIPS CPU based on technology it acquired last year. The new CPU implements the MIPS64 R6 ISA and SIMD extensions but adds support for AI data types.

Designers can configure WaveTensor with 64 INT4 or INT8 multiply-accumulate units (MACs) in a 4x4x4 structure, or 512 MACs in an 8x8x8 array. The WaveTensor tiles also implement other common neural-network functions, such as pooling and activations, but the company withheld details. Although WaveFlow tiles retain the same 16-PE arrangement as the original DPU, the new version provides much greater multiply-accumulate (MAC) performance. Along with the PEs, each cluster integrates eight 32-bit ALUs that incorporate MAC units, along with support for SIMD operations. For inference, the ALUs/MACs support INT8, INT16, and INT32 datatypes.

In its first release, TritonAI will enable inference using integer operations; the company says a future version will support training with FP32 and Bfloat16 data, although it hasn’t committed to a schedule for that version. In 7nm technology, Wave expects the TritonAI tile architecture will scale as high as 1,024 trillion operations per second (TOPS) and achieve power efficiency of 8.3 TOPS per watt. It rolled out TritonAI at the recent Linley Processor Conference, and it plans to offer the inference engine for licensing in 3Q19.

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